H8SX1668R Datasheet, PDF (755/1504 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 14 16-Bit Timer Pulse Unit (TPU)
Initial
Bit Bit Name value R/W Description
3 TGIED 0
R/W TGR Interrupt Enable D
Enables/disables interrupt requests (TGID) by the TGFD bit
when the TGFD bit in TSR is set to 1 in channels 0 and 3.
In channels 1, 2, 4, and 5, bit 3 is reserved. It is always read as
0 and cannot be modified.
0: Interrupt requests (TGID) by TGFD bit disabled
1: Interrupt requests (TGID) by TGFD bit enabled
2 TGIEC 0
R/W TGR Interrupt Enable C
Enables/disables interrupt requests (TGIC) by the TGFC bit
when the TGFC bit in TSR is set to 1 in channels 0 and 3.
In channels 1, 2, 4, and 5, bit 2 is reserved. It is always read as
0 and cannot be modified.
0: Interrupt requests (TGIC) by TGFC bit disabled
1: Interrupt requests (TGIC) by TGFC bit enabled
1 TGIEB 0
R/W TGR Interrupt Enable B
Enables/disables interrupt requests (TGIB) by the TGFB bit
when the TGFB bit in TSR is set to 1.
0: Interrupt requests (TGIB) by TGFB bit disabled
1: Interrupt requests (TGIB) by TGFB bit enabled
0 TGIEA 0
R/W TGR Interrupt Enable A
Enables/disables interrupt requests (TGIA) by the TGFA bit
when the TGFA bit in TSR is set to 1.
0: Interrupt requests (TGIA) by TGFA bit disabled
1: Interrupt requests (TGIA) by TGFA bit enabled
Note: * The bit 7 in TIER of unit 1 is a reserved bit. This bit is always read as 0 and the initial
value should not be changed.
14.3.5 Timer Status Register (TSR)
TSR indicates the status of each channel. The TPU has six TSR registers, one for each channel.
Bit
Bit Name
Initial Value
R/W
7
TCFD
1
R
6
5
4

TCFU
TCFV
1
0
0

R/(W)*
R/(W)*
Note: * Only 0 can be written to bits 5 to 0, to clear flags.
3
TGFD
0
R/(W)*
2
TGFC
0
R/(W)*
1
TGFB
0
R/(W)*
0
TGFA
0
R/(W)*
Rev. 2.00 Sep. 24, 2008 Page 723 of 1468
REJ09B0412-0200