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| H8SX1668R Datasheet, PDF (618/1504 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series | |||
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Section 12 Data Transfer Controller (DTC)
12.5.9 Number of DTC Execution Cycles
Table 12.9 shows the execution status for a single DTC data transfer, and table 12.10 shows the
number of cycles required for each execution.
Table 12.9 DTC Execution Status
Mode
Vector
Read
I
Transfer
Information
Read
J
Transfer
Information
Write
L
Data Read
L
Data Write
M
Internal
Operation
N
Normal 1 0*1 4*2 3*3 0*1 3*2.3 2*4 1*5 3*6 2*7 1 3*6 2*7 1 1 0*1
Repeat 1 0*1 4*2 3*3 0*1 3*2.3 2*4 1*5 3*6 2*7 1 3*6 2*7 1 1 0*1
Block 1
0*1 4*2 3*3 0*1 3*2.3 2*4 1*5 3â¢P*6 2â¢P*7 1â¢P 3â¢P*6 2â¢P*7 1â¢P 1
0*1
transfer
[Legend]
P: Block size (CRAH and CRAL value)
Note: 1. When transfer information read is skipped
2. In full address mode operation
3. In short address mode operation
4. When the SAR or DAR is in fixed mode
5. When the SAR and DAR are in fixed mode
6. When a longword is transferred while an odd address is specified in the address
register
7. When a word is transferred while an odd address is specified in the address register or
when a longword is transferred while address 4n + 2 is specified
Rev. 2.00 Sep. 24, 2008 Page 586 of 1468
REJ09B0412-0200
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