H8SX1668R Datasheet, PDF (586/1504 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 11 EXDMA Controller (EXDMAC)
Interrupt source settings are made individually with the interrupt enable bits in the registers for the
relevant channels. The transfer counter's transfer end interrupt is enabled or disabled by means of
the DTIE bit in EDMDR, the transfer size error interrupt by means of the TSEIE bit in EDMDR,
the repeat size end interrupt by means of the RPTIE bit in EDACR, the source address extended
repeat area overflow interrupt by means of the SARIE bit in EDACR, and the destination address
extended repeat area overflow interrupt by means of the DARIE bit in EDACR.
The transfer end interrupt by the transfer counter occurs when the DTIE bit in EDMDR is set to 1,
the EDTCR becomes 0 by transfer, and then the DTIF bit in EDMDR is set to 1.
Interrupts other than the transfer end interrupt by the transfer counter occurs when the
corresponding interrupt enable bit is set to 1, the condition for that interrupt is satisfied, and then
the ESIF bit in EDMDR is set to 1.
The transfer size error interrupt occurs when the EDTCR value is smaller than the data access size
and a data-access-size transfer for one request cannot be performed for a transfer request. In block
transfer mode, the block size is compared to the EDTCR value to determine a transfer size error.
In cluster transfer mode, the cluster size is compared to the EDTCR value to determine a transfer
size error.
The repeat size end interrupt occurs when the next transfer request is generated after the end of a
repeat size transfer in repeat transfer mode. When the repeat area is not set in the address register,
transfer can be aborted periodically based on the set repeat size value. If the transfer end interrupt
by the transfer counter occurs at the same time, the ESIF bit is set to 1.
The source/destination address extended repeat area overflow interrupt occurs when the addresses
overflow the specified extended repeat area. If the transfer end interrupt by the transfer counter
occurs at the same time, the ESIF bit is set to 1.
Figure 11.70 shows the block diagram of various interrupts and their interrupt flags. The transfer
end interrupt can be cleared either by clearing the DTIF or ESIF bit to 0 in EDMDR within the
interrupt handling routine, or by re-setting the address registers and then setting the DTE bit to 1
in EDMDR to perform transfer continuation processing. An example of the procedure for clearing
the transfer end interrupt and restarting transfer is shown in figure 11.71.
Rev. 2.00 Sep. 24, 2008 Page 554 of 1468
REJ09B0412-0200