H8SX1668R Datasheet, PDF (550/1504 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 11 EXDMA Controller (EXDMAC)
(4) EDREQ Pin Low Level Activation Timing
Figure 11.37 shows an example of single address mode transfer activated by the EDREQ pin low
level.
EDREQ pin sampling is performed in each cycle starting at the next rise of Bφ after the end of the
DTE bit write cycle.
When a low level is sampled at the EDREQ pin while acceptance of a transfer request via the
EDREQ pin is possible, the request is held within the EXDMAC. Then when activation is initiated
within the EXDMAC, the request is cleared. After the end of the single cycle, acceptance resumes
and EDREQ pin low level sampling is performed again. This sequence of operations is repeated
until the end of the transfer.
Bφ
EDREQ
Address bus
EDACK
EXDMA control Idle
Bus
release
EXDMA single
Bus
release
Bus
EXDMA single _release
Transfer source/
Transfer destination
Single Idle
Transfer source/
Transfer destination
Single Idle
Channel
Request ^{Request clearance period}
Request
Request clearance period
Minimum 3 cycles
Minimum 3 cycles
[1]
[2]
[3]
[4]
[5]
[6]
[7]
Acceptance resumed
Acceptance resumed
[1] Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of Bφ, and request is held.
[2], [5] Request is cleared at end of next bus cycle, and activation is started in EXDMAC.
[3], [6] EXDMA cycle starts.
[4], [7] Acceptance is resumed after completion of single cycle.
(As in [1], EDREQ pin low level is sampled at rise of Bφ, and request is held.)
Figure 11.37 Example of Single Address Mode Transfer Activated
by EDREQ Pin Low Level
Rev. 2.00 Sep. 24, 2008 Page 518 of 1468
REJ09B0412-0200