H8SX1668R Datasheet, PDF (56/1504 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 1 Overview
Classification
Address bus
Data bus
Bus control
Pin Name
A23 to A0
D15 to D0
BREQ
BREQO
I/O
Output
Input/
output
Input
Output
BACK
BS-A/BS-B
AS
Output
Output
Output
AH
Output
RD
Output
RD/WR-A/RD/WR-B Output
LHWR
Output
LLWR
Output
LUB
Output
LLB
Output
Description
Output pins for the address bits.
Input and output for the bidirectional data bus. These pins
also output addresses when accessing an address–data
multiplexed I/O interface space.
External bus-master modules assert this signal to request
the bus.
Internal bus-master modules assert this signal to request
access to the external space via the bus in the external bus
released state.
Bus acknowledge signal, which indicates that the bus has
been released.
Indicates the start of a bus cycle.
Strobe signal which indicates that the output address on the
address bus is valid in access to the basic bus interface or
byte control SRAM interface space.
This signal is used to hold the address when accessing the
address-data multiplexed I/O interface space.
Strobe signal which indicates that reading from the basic bus
interface space is in progress.
Indicates the direction (input or output) of the data bus.
Strobe signal which indicates that the higher-order byte (D15
to D8) is valid in access to the basic bus interface space.
Strobe signal which indicates that the lower-order byte (D7 to
D0) is valid in access to the basic bus interface space.
Strobe signal which indicates that the higher-order byte (D15
to D8) is valid in access to the byte control SRAM interface
space.
Strobe signal which indicates that the lower-order byte (D7 to
D0) is valid in access to the byte control SRAM interface
space.
Rev. 2.00 Sep. 24, 2008 Page 24 of 1468
REJ09B0412-0200