H8SX1668R Datasheet, PDF (688/1504 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 13 I/O Ports
Port
P3 4
3
2
1
0
P6 5
Output
Output
Specification Signal
Signal Name Name
ETEND3_OE ETEND3
TEND1B_OE TEND1
TIOCA1_OE TIOCA1
PO12_OE
TIOCD0_OE
PO12
TIOCD0
PO11_OE
PO11
EDACK2_OE EDACK2
DACK0B_OE DACK0
TIOCC0_OE TIOCC0
PO10_OE
PO10
ETEND2_OE ETEND2
TEND0B_OE TEND0
TIOCB0_OE TIOCB0
PO9_OE
TIOCA0_OE
PO9
TIOCA0
PO8_OE
PO8
EDACK1B_OE EDACK1
DACK3_OE DACK3
TMO3_OE TMO3
Signal Selection
Register Settings
Peripheral Module Settings
PFCR8.EDMAS3[A,B] = SYSCR.EXPE = 1, EDMDR_3.ETENDE = 1
00
PFCR7.DMAS1[A,B] = DMDR_1.TENDE = 1
01
TPU.TIOR_1.IOA3 = 0,
TPU.TIOR_1.IOA[1,0] = 01/10/11
NDERH.NDER12 = 1
TPU.TMDR.BFB = 0,
TPU.TIORL_0.IOD3 = 0,
TPU.TIORL_0.IOD[1,0] = 01/10/11
NDERH.NDER11 = 1
PFCR8.EDMAS2[A,B] = SYSCR.EXPE = 1, EDACR_2.AMS = 1,
00
EDMDR_2.EDACKE = 1
PFCR7.DMAS0[A,B] = DMAC.DACR.AMS = 1,
01
DMDR_0.DACKE = 1
TPU.TMDR.BFA = 0,
TPU.TIORL_0.IOC3 = 0,
TPU.TIORL_0.IOD[1,0] = 01/10/11
NDERH.NDER10 = 1
PFCR8.EDMAS2[A,B] = SYSCR.EXPE = 1, EDMDR_2.ETENDE = 1
00
PFCR7.DMAS0[A,B] = DMDR_0.TENDE = 1
01
TPU.TIORH_0.IOB3 = 0,
TPU.TIORH_0.IOB[1,0] = 01/10/11
NDERH.NDER9 = 1
TPU.TIORH_0.IOA3 = 0,
TPU.TIORH_0.IOA[1,0] = 01/10/11
NDERH.NDER8 = 1
PFCR8.EDMAS1[A,B] = SYSCR.EXPE = 1, EDACR_1.AMS = 1,
01
EDMDR_1.EDACKE = 1
PFCR7.DMAS3[A,B] = DMAC.DACR_3.AMS = 1,
01
DMDR_3.DACKE = 1
TMR.TCSR_3.OS[3,2] = 01/10/11 or
TMR.TCSR_3.OS[1,0] = 01/10/11
Rev. 2.00 Sep. 24, 2008 Page 656 of 1468
REJ09B0412-0200