RX113_15 Datasheet, PDF (84/121 Pages) Renesas Technology Corp – Renesas MCUs

RX113 Group
5. Electrical Characteristics
Table 5.34 Timing of On-Chip Peripheral Modules (5)
Conditions: VCC = AVCC0 = VCC_USB = 2.7 to 3.6 V, VSS = AVSS0 = VSS_USB = 0 V, fPCLKB ≤ 32 MHz,
T_a = –40 to +105°C
Item
Symbol
Min.
Simple I²C
SDA0 input rise time
(Standard mode) _{SDA0 input fall time}
t_Sr
—
t_Sf
—
SDA0 input spike pulse removal time
t_SP
0
Data input setup time
t_SDAS
250
Data input hold time
t_SDAH
0
SCL0, SDA0 capacitive load
C_b
—
Simple I²C
(Fast mode)
SCL0, SDA0 input rise time
SCL0, SDA0 input fall time
t_Sr
—
t_Sf
—
SCL0, SDA0 input spike pulse removal time t_SP
0
Data input setup time
t_SDAS
100
Data input hold time
t_SDAH
0
SCL0, SDA0 capacitive load
C_b
—
Max.
1000
300
4 × t_pcyc*¹
—
—
400
300
300
4 × t_pcyc*¹
—
—
400
Unit
Test
Conditions
ns Figure 5.49
ns
ns
ns
ns
pF
ns Figure 5.49
ns
ns
ns
ns
pF
Note: t_Pcyc: PCLK cycle
Note 1. This applies when the SMR.CKS[1:0] bits = 00b and the SNFR.NFCS[2:0] bits = 010b while the SNFR.NFE bit = 1 and the
digital filter is enabled.
Table 5.35 Timing of On-Chip Peripheral Modules (6)
Conditions: VCC = AVCC0 = VCC_USB = 1.8 to 3.6 V, VSS = AVSS0 = VSS_USB = 0 V, fPCLKB ≤ 32 MHz,
T_a = –40 to +105°C
Item
Symbol
Min.
Max.
Unit
SSI
AUDIO_MCLK input
2.7 V or above
t_AUDIO
1
frequency
1.8 V or above
1
Output clock cycle
t_O
250
Input clock cycle
t_I
250
Clock high pulse width
t_HC
0.4
Clock low pulse width
t_LC
0.4
Clock rise time
t_RC
—
Data delay time
2.7 V or above
t_DTR
—
1.8 V or above
—
Setup time
2.7 V or above
t_SR
65
1.8 V or above
90
Hold time
t_HTR
40
WS changing edge SSIDATA output delay
t_DTRW
—
25
MHz
4
—
ns
—
ns
0.6
to, ti
0.6
to, ti
20
ns
65
ns
105
—
ns
—
—
ns
105
ns
Test
Conditions
Figure 5.50
Figure 5.51
Figure 5.52
Figure 5.53
R01DS0216EJ0102 Rev.1.02
Dec 01, 2014
Page 84 of 121