RX113_15 Datasheet, PDF (8/121 Pages) Renesas Technology Corp – Renesas MCUs

RX113 Group
1.3 Block Diagram
Figure 1.2 shows a block diagram.
1. Overview
ROM
RAM
RX CPU
Clock
generation
circuit
ICUb
DTCa
E2 DataFlash
TMR × 2 channels (unit 0)
TMR × 2 channels (unit 1)
IWDTa
ELC
CRC
SCIe × 7 channels
(including IrDA × 1 channel)
SCIf × 1 channel
RSPI × 1 channel
RIIC × 1 channel
MTU2a × 6 channels
POE2a
SSI
USB 2.0 host/function module
CMT × 2 channels (unit 0)
CMT × 2 channels (unit 1)
RTCc
12-bit A/D converter × 17 channels
Temperature sensor
12-bit D/A converter × 2 channels
DOC
Comparator B
LCD controller/driver
CAC
CTSU
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 9
Port A
Port B
Port C
Port D
Port E
Port F
Port H
Port J
ICUb:
DTCa:
TMR:
IWDTa:
ELC:
CRC:
SCIe/SCIf:
RSPI:
RIIC:
Interrupt controller
Data transfer controller
8-bit timer
Independent watchdog timer
Event link controller
CRC (cyclic redundancy check) calculator
Serial communications interface
Serial peripheral interface
I²C bus interface
MTU2a: Multi-function timer pulse unit 2
POE2a: Port output enable 2
SSI: Serial sound interface
CMT: Compare match timer
RTCc: Realtime clock
DOC: Data operation circuit
CAC: Clock frequency accuracy measurement circuit
CTSU: Capacitive touch sensing unit
Figure 1.2
Block Diagram
R01DS0216EJ0102 Rev.1.02
Dec 01, 2014
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