RX113_15 Datasheet, PDF (114/121 Pages) Renesas Technology Corp – Renesas MCUs

RX113 Group
5. Electrical Characteristics
5.14 E2 DataFlash Characteristics
Table 5.63 E2 DataFlash Characteristics (1)
Item
Reprogramming/erasure cycle*¹
Data hold time
After 10000 times of N_DPEC
After 100000 times of N_DPEC
After 1000000 times of N_DPEC
Symbol
N_DPEC
t_DDRP
Min.
100000
20*^2, *³
5*^2, *³
—
Typ.
1000000
—
—
1*^2, *³
Max.
—
—
—
—
Unit
Times
Year
Year
Year
Conditions
T_a = +85°C
T_a = +25°C
Note 1. The reprogram/erase cycle is the number of erasing for each block. When the reprogram/erase cycle is n times (n = 100000),
erasing can be performed n times for each block. For instance, when 1-byte programming is performed 1000 times for different
addresses in 1-Kbyte block and then the entire block is erased, the reprogram/erase cycle is counted as one. However,
programming the same address for several times as one erasing is not enabled (overwriting is prohibited).
Note 2. Characteristics when using the flash memory programmer.
Note 3. These results are obtained from reliability testing.
Table 5.64 E2 DataFlash Characteristics (2)
: high-speed operating mode
Conditions: VCC = AVCC0 = VCC_USB = 2.7 to 3.6 V, VSS = AVSS0 = USB_VSS = 0 V
Temperature range for the programming/erasure operation: T_a = –40 to +105°C
Item
Programming time
1-byte
Erasure time
1-Kbyte
Blank check time
1-byte
1-Kbyte
Erase operation forcible stop time
DataFlash STOP recovery time
Symbol
t_DP1
t_DE1K
t_DBC1
t_DBC1K
t_DSED
t_DSTOP
FCLK = 4 MHz
Min.
Typ.
—
86
—
17.4
—
—
—
—
—
—
5
—
Max.
761
456
48
1.58
21.5
—
FCLK = 32 MHz
Unit
Min.
Typ. Max.
—
40.5
374
μs
—
6.15
228
ms
—
—
15.9
μs
—
—
0.127 ms
—
—
12.8
μs
5
—
—
μs
Note:
Note:
Note:
Does not include the time until each operation of the flash memory is started after instructions are executed by software.
The lower-limit frequency of FCLK is 1 MHz during programming or erasing of the flash memory. When using FCLK at below
4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set.
The frequency accuracy of FCLK should be ±3.5%. Confirm the frequency accuracy of the clock source.
Table 5.65 E2 DataFlash Characteristics (3)
: middle-speed operating mode
Conditions: VCC = AVCC0 = VCC_USB = 1.8 to 3.6 V, VSS = AVSS0 = USB_VSS = 0 V
Temperature range for the programming/erasure operation: T_a = –40 to +105°C
Item
Programming time
1-byte
Erasure time
1-Kbyte
Blank check time
1-byte
1-Kbyte
Erase operation forcible stop time
DataFlash STOP recovery time
Symbol
t_DP1
t_DE1K
t_DBC1
t_DBC1K
t_DSED
t_DSTOP
FCLK = 4 MHz
Min.
Typ.
—
126
—
17.5
—
—
—
—
—
—
720
—
Max.
1160
457
78
1.61
33.5
—
FCLK = 8 MHz
Unit
Min.
Typ. Max.
—
85.4
818
μs
—
7.76
259
ms
—
—
50
μs
—
—
0.369 ms
—
—
25.5
μs
720
—
—
ns
Note:
Note:
Note:
Does not include the time until each operation of the flash memory is started after instructions are executed by software.
The lower-limit frequency of FCLK is 1 MHz during programming or erasing of the flash memory. When using FCLK at below
4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set.
The frequency accuracy of FCLK should be ±3.5%. Confirm the frequency accuracy of the clock source.
R01DS0216EJ0102 Rev.1.02
Dec 01, 2014
Page 114 of 121