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RX113_15 Datasheet, PDF (81/121 Pages) Renesas Technology Corp – Renesas MCUs
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RX113 Group
5. Electrical Characteristics
Table 5.31 Timing of On-Chip Peripheral Modules (2)
Conditions: VCC = AVCC0 = VCC_USB = 1.8 to 3.6 V, VSS = AVSS0 = VSS_USB = 0 V, Ta = –40 to +105°C, C = 30 pF
Item
Symbol
Min.
Max.
Unit
Test
Conditions
RSPI RSPCK clock cycle
Master
Slave
tSPcyc
2
8
4096
4096
tPcyc*1 Figure 5.42
RSPCK clock
high pulse width
Master
tSPCKWH (tSPcyc – tSPCKr –
—
ns
tSPCKf)/2 – 3
Slave
(tSPcyc – tSPCKr –
—
tSPCKf)/2
RSPCK clock
low pulse width
Master
tSPCKWL (tSPcyc – tSPCKr–
—
ns
tSPCKf)/2 – 3
Slave
(tSPcyc – tSPCKr –
—
tSPCKf)/2
RSPCK clock
rise/fall time
Output 2.7 V or above
1.8 V or above
tSPCKr,
—
tSPCKf
—
10
ns
15
Input
—
1
μs
Data input setup time Master 2.7 V or above
tSU
1.8 V or above
Slave
Data input hold time Master RSPCK set to a division
tH
ratio other than PCLKB
divided by 2
10
30
25 – tPcyc
tPcyc
—
ns Figure 5.43
—
to
Figure 5.48
—
—
ns
RSPCK set to PCLKB
tHF
0
—
divided by 2
SSL setup time
Slave
Master
SSL hold time
Slave
Master
Slave
Data output delay time Master 2.7 V or above
1.8 V or above
tH
tLEAD
tLAG
tOD
20 + 2 × tPcyc
–30 + N*2 ×
tSPcyc
2
–30 + N*3 ×
tSPcyc
2
—
—
—
—
ns
—
tPcyc
—
ns
—
tPcyc
14
ns
30
Data output hold time
Slave 2.7 V or above
1.8 V or above
Master 2.7 V or above
1.8 V or above
—
3 × tPcyc + 65
—
3 × tPcyc +105
tOH
0
—
ns
–20
—
Slave
0
—
Successive
transmission delay
time
MOSI and MISO rise/
fall time
Master
Slave
Output 2.7 V or above
1.8 V or above
tTD
tSPcyc + 2 × tPcyc 8 × tSPcyc + 2 ×
ns
tPcyc
4 × tPcyc
—
tDr, tDf
—
10
ns
—
20
Input
—
1
μs
SSL rise/fall time
Output
Input
tSSLr,
—
tSSLf
—
20
ns
1
μs
Slave access time
2.7 V or above
1.8 V or above
tSA
—
—
6
tPcyc Figure 5.47,
7
Figure 5.48
Slave output release time
2.7 V or above
1.8 V or above
tREL
—
—
5
tPcyc
6
Note 1. tPcyc: PCLK cycle
Note 2. N: An integer from 1 to 8 that can be set by the RSPI clock delay register (SPCKD)
Note 3. N: An integer from 1 to 8 that can be set by the RSPI slave select negation delay register (SSLND)
R01DS0216EJ0102 Rev.1.02
Dec 01, 2014
Page 81 of 121
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