RX113_15 Datasheet, PDF (80/121 Pages) Renesas Technology Corp – Renesas MCUs

RX113 Group
5. Electrical Characteristics
5.3.5
Timing of On-Chip Peripheral Modules
Table 5.30 Timing of On-Chip Peripheral Modules (1)
Conditions: VCC = AVCC0 = VCC_USB = 1.8 to 3.6 V, VSS = AVSS0 = VSS_USB = 0 V, T_a = –40 to +105°C
Item
Symbol
Min.
Max.
Unit*¹
Test
Conditions
I/O ports
Input data pulse width
t_PRW
1.5
— t_Pcyc Figure 5.33
MTU2
Input capture input pulse width
Single-edge setting
t_TICW
1.5
— t_Pcyc Figure 5.34
Both-edge setting
2.5
—
Timer clock pulse width
Single-edge setting t_TCKWH,
1.5
Both-edge setting
t_TCKWL
2.5
— t_Pcyc Figure 5.35
—
Phase counting mode
2.5
—
POE
TMR
POE# input pulse width
Timer clock pulse width
t_POEW
1.5
Asynchronous
t_TMCWH,
1.5
Clock synchronous
t_TMCWL
2.5
— t_Pcyc Figure 5.36
— t_Pcyc Figure 5.37
—
SCI
Input clock cycle
Asynchronous
t_Scyc
4
— t_Pcyc Figure 5.38
Clock synchronous
6
—
Input clock pulse width
Input clock rise time
Input clock fall time
Output clock cycle
t_SCKW
0.4
0.6 t_Scyc
t_SCKr
—
20 ns
t_SCKf
—
20 ns
Asynchronous
t_Scyc
16
— t_Pcyc Figure 5.39
Clock synchronous
4
—
C = 30 pF
Output clock pulse width
Output clock rise time
Output clock fall time
Transmit data delay Clock synchronous
time (master)
t_SCKW
0.4
0.6 t_Scyc
t_SCKr
—
20 ns
t_SCKf
—
20 ns
t_TXD
—
40 ns
Transmit data delay Clock
2.7 V or above
time (slave)
synchronous _{1.8 V or above}
—
65 ns
—
100 ns
Receive data setup Clock
2.7 V or above
time (master)
synchronous _{1.8 V or above}
t_RXS
65
— ns
90
— ns
Receive data setup Clock synchronous
time (slave)
40
— ns
Receive data hold Clock synchronous
time
t_RXH
40
— ns
A/D converter Trigger input pulse width
CAC
CACREF input pulse width
CLKOUT
CLKOUT pin output cycle*⁴
t_Pcyc ≤ t_cac*²
t_TRGW
1.5
—
t_CACREF 4.5 t_cac + 3 t_Pcyc —
t_Pcyc > t_cac*²
5 t_cac + 6.5 t_Pcyc
VCC = 2.7 V or above t_Ccyc
125
—
VCC = 1.8 V or above
250
t_Pcyc Figure 5.40
ns
ns Figure 5.41
CLKOUT pin high pulse width*³
VCC = 2.7 V or above t_CH
VCC = 1.8 V or above
35
— ns
70
CLKOUT pin low pulse width*³
VCC = 2.7 V or above t_CL
VCC = 1.8 V or above
35
— ns
70
CLKOUT pin output rise time
VCC = 2.7 V or above t_Cr
VCC = 1.8 V or above
—
15 ns
30
CLKOUT pin output fall time
VCC = 2.7 V or above t_Cf
VCC = 1.8 V or above
—
15 ns
30
Note 1. t_Pcyc: PCLK cycle
Note 2. t_cac: CAC count clock source cycle
Note 3. When the LOCO is selected as the clock output source (CKOCR.CKOSEL[2:0] bits = 000b), set the clock output division ratio
selection to divided by 2 (CKOCR.CKODIV[2:0] bits = 001b).
Note 4. When the XTAL external clock input or an oscillator is used with divided by 1 (CKOCR.CKOSEL[2:0] bits = 010b and
CKOCR.CKODIV[2:0] bits = 000b) to output from CLKOUT, the above should be satisfied with an input duty cycle of 45 to 55%.
R01DS0216EJ0102 Rev.1.02
Dec 01, 2014
Page 80 of 121