38K0 Datasheet, PDF (80/133 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

38K0 Group
Reset
XIN 8-divide mode
f(φ) = 0.75 MHz
CM7 = 0
CM6 = 0
CM5 = 0
PLLCON [4:3] = 00
CM6
“0”←→“1”
XIN 4-divide mode
f(φ) = 1.5 MHz
CM7 = 0
CM6 = 0
CM5 = 0
PLLCON [4:3] = xx
(arbitrary)
XIN 2-divide mode
f(φ) = 3.0 MHz
CM7 = 1
CM6 = 0
CM5 = 0
PLLCON [4:3] = xx
(arbitrary)
CM6
“0”←→“1”
XIN through mode
f(φ) = 1.5 MHz
CM7 = 0
CM6 = 0
CM5 = 0
PLLCON [4:3] = xx
(arbitrary)
Note:
Set PLLCON [4:3] = 10 before
switching the system clock from XIN
to fSYN.
f(SYN) 2-divide mode
f(φ) = 6.0 MHz
CM7 = 1
CM6 = 0
CM5 = 1
PLLCON [4:3] = 10
CM6
“0”←→“1”
f(SYN) through mode
f(φ) = 12.0 MHz
CM7 = 1
CM6 = 1
CM5 = 1
PLLCON [4:3] = 10
CM5
“0”←→“1”
CM6
“0”←→“1”
Note:
Set PLLCON [4:3] = 00 before switching
the system clock from XIN to fSYN.
CM5
“0”←→“1”
CM6
“0”←→“1”
Note:
Set PLLCON [4:3] = 01 before switching
the system clock from XIN to fSYN.
f(SYN) through mode
f(φ) = 6.0 MHz
CM7 = 1
CM6 = 1
CM5 = 1
PLLCON [4:3] = 00
f(SYN) through mode
f(φ) = 8.0 MHz
CM7 = 1
CM6 = 1
CM5 = 1
PLLCON [4:3] = 01
Under planning
CM5
“0”←→“1”
Note:
Set PLLCON [4:3] = 00 before switching
the system clock from XIN to fSYN.
CM5
“0”←→“1”
Note:
Set PLLCON [4:3] = 01 before switching
the system clock from XIN to fSYN.
Notes 1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the modes directly
without an allow.)
2 : Set the USB clock (fUSB) to 48 MHz when switching the system clock to fSYN.
3 : Do not change a division ratio of USB clock when using fSYN as the system clock.
4 : See section “PLL CIRCUIT” in details for enabling/disabling PLL operation and usage notes of fSYN.
5 : Set the system clock to XIN when entering STOP mode.
6 : In all modes, switching to WAIT mode is possible. When it is released, the MCU returns to the original mode. In
WAIT mode the timers can operate.
Remarks : This diagram assumes that the 6 MHz signals are applied to XIN pin.
Fig. 115 State transitions of clock
Rev.3.00 Oct 05, 2006 page 80 of 129
REJ03B0192-0300