38K0 Datasheet, PDF (58/133 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

38K0 Group
EXB Related Registers
The EXB related registers are shown below.
b7
00 000
b0
EXB interrupt source enable register (EXBICON) [address 003016]
(Note)
Bit symbol
RXB_ENB
TXB_ENB
MC_ENB
b7:b3
Bit name
Function
At reset _{R W}
H/W S/W
CPU channel receive enable bit 0 : Operation disabled (Interrupt disabled)
0 – OO
1 : Operation enabled (Receive buffer full interrupt enabled)
CPU channel transmit enable bit 0 : Operation disabled (Interrupt disabled)
0 – OO
1 : Operation enabled (Transmit buffer empty interrupt enabled)
Memory channel operation
0 : Operation disabled (Memory channel operation end 0 – O O
enable bit
interrupt disabled)
1 : Operation enabled (Memory channel operation end
interrupt disabled)
Not used
Write “0” when writing.
– – OO
“0” is read when reading.
–: State remaining
Note: Do not set each bit simultaneously.
Fig. 79 Structure of EXB interrupt source enable register
b7
0000
b0
EXB interrupt source register (EXBIREQ) [address 003116] (Note 1)
Bit symbol
Bit name
RXB_FULL Receive buffer full bit
TXB_EMPTY Transmit buffer empty bit
MC_STS
[1:0]
(Note 2)
Memory channel status bits
b7:b4
Not used
Function
0 : Receive buffer empty
1 : Receive buffer full
0 : Transmit buffer full
1 : Transmit buffer empty
b3b2
0 0 : Memory channel operation stopped
0 1 : Memory channel being operating;
No external access
1 0 : Memory channel being operating;
External accessing
1 1 : Memory channel operation end; Memory
channel operation end interrupt generated
Write “0” when writing.
“0” is read when reading.
At reset _{R W}
H/W S/W
0 0 O–
(Note 3)
0 0 O–
(Note 4)
0 0 O–
– – OO
–: State remaining
Notes 1: When the the ExA1 pin control bit of external I/O configuration register is “1”, the external MCU bus can read this
register contents by setting the ExA1 pin to “H”.
2: The memory channel status bits indicate the status of memory channel. In MC_ENB = “0” these bits are always
“002”. When the memory channel operation ends, these bits are set to “112” and the memory channel operation
end interrupt is generated.
These bits can be read out during operation, so that it will show that whether the external MCU bus is accessing
or not.
3: This bit is cleared to “0” when reading the transmit/receive buffer register in the CPU channel receive enable bit =
“1” or when the CPU channel receive enable bit is “0”.
4: This bit is cleared to “0” when writing to the transmit/receive buffer register in the CPU channel transmit enable bit
= “1” or when the CPU channel transmit enable bit is “0”.
Fig. 80 Structure of EXB interrupt source register
Rev.3.00 Oct 05, 2006 page 58 of 129
REJ03B0192-0300