38K0 Datasheet, PDF (63/133 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

38K0 Group
EXB Operation Timing Diagram
(1) CPU Channel Receiving Operation
CPU channel receiving operation is shown bellow.
➀
Address ExA0
Chip select ExCS
Read ExRD
Write ExWR
Data DQ0 to DQ7
➁
A0 = “1”
CS = “0”
➁
#0
➂
A0 = “1”
CS = “0”
#1
Internal clock φ
Interrupt request ExINT
[RxB_RDY]
Receive buffer full bit RXB_FULL
RxB_RDY
RxB_RDY
Receive buffer RXBUF
#0
#1
Transmit buffer TXBUF
➀
CPU channel receive enable bit
RXB_ENB
Receive buffer read
➂
<Initial setting>
External I/O configuration register
INT_CTR[3:1] (P33/ExINT pin control) = 0012 (RxB_RDY interrupt)
<Operation start>
EXB interrupt source enable register
RXB_ENB (CPU channel receive enable) = “1” (Receive buffer full interrupt enabled)
➀ Writing the command for enabling operation makes RXB_RDY assertion and the P33/ExINT pin goes to “L”.
If the CPU channel receive enable bit (RXB_ENB) is “0”, both the receive buffer full bit (RXB_FULL) and the receive buffer ready signal (RxB_RDY) to an
external are inactive.
➁ When a write operation is performed from an external MCU bus in the condition of ExCS = “L” and WxA0 = “H”, it will result in as follows:
• The data is written into the receive buffer (RXBUF)
• Negation of the receive buffer ready signal (RxB_RDY) to an external is made
• The RXB_FULL interrupt is generated.
➂ When the CPU reads out the receive buffer (RXBUF) with an interrupt processing program, the receive buffer full bit (RXB_FULL) is cleared to “0”.
Fig. 92 CPU channel receiving operation
Rev.3.00 Oct 05, 2006 page 63 of 129
REJ03B0192-0300