38K0 Datasheet, PDF (65/133 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

38K0 Group
(3) Memory Channel Receiving Operation (1)-
Cycle Mode
Memory channel receiving operation (1) is shown bellow.
➀
Address ExA0
➁
➂
➃
A0 = “0”
➁’
➂’
➄
A0 = “0”
Chip select ExCS
DMA acknowledge
ExDACK
Read ExRD
CS = “0”
CS = “0”
Write ExWR
Data DQ0 to DQ7
Internal clock φ
DMA request
ExDREQ
mWR detection
mWR detection
#0
Mch_req
#1
Mch_req
Receive buffer RXBUF
#0
#1
Operation enabled
Main sequencer
Memory channel operation
end interrupt
Internal memory access
➀
0
1
2
3
req
5
req
Memory address
Counter end
010016
010116
010216
Acknowledgment of
internal memory access
ack
➃
ack
➄
<Initial setting>
External I/O configuration register
Memory channel operation mode register
Memory address counter
End address register
Set as necessary.
MC_DIR[1:0] (Memory channel direction control) = 012 (Receive mode)
Burst (burst) = “0” (Cycle mode)
(Example) 010016
(Example) 010116
<Operation start command>
EXB interrupt source enable register
MC_ENB (Memory channel operation enable) = “1” (Operation start)
➀ In the memory channel receive mode when the command for enabling operation is written, operation starts (main sequencer starts) and assertion of the
memory channel request which synchronized with a rise of φ is made.
➁ When the external MCU bus is in the condition of ExCS = “L” and ExA0 = “L” or a fall of ExWR is detected in the condition of ExDACK = “L”, negation of the
memory channel request which synchronized with a rise of φ is made.
➂ When a rise of ExWR is detected, an internal memory access sequence which synchronized with a rise of φ is activated and a data is written in the internal
memory within two clocks at a minimum.
➃ The memory address counter is increased simultaneously at write completion and assertion of the next memory channel request is made.
➄ When the write operation to the end address has been completed, the memory address counter is increased, but assertion of the next memory channel
request is not made and the memory channel operation end interrupt is generated.
Fig. 94 Memory channel receiving operation (1)
Rev.3.00 Oct 05, 2006 page 65 of 129
REJ03B0192-0300