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38K0 Datasheet, PDF (67/133 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER | |||
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38K0 Group
(5) Memory Channel Receiving Operation (3)-
Burst Mode (Terminal Count)
Memory channel receiving operation (3) is shown bellow.
Address ExA0
A0 = âxâ
Chip select ExCS
DMA acknowledge
ExDACK
Terminal count ExTC
CS = â1â
Dack = â0â
Write ExWR
Data DQ0 to DQ7
Internal clock Ï
DMA request
ExDREQ
mWR detection
#0
Mch_req
mWR detection
Receive buffer RxBuf
mTC detection
TC synchronizing
TC end
Operation enabled
Main sequencer
0
1
2
Memory channel operation
end interrupt
Internal memory access
ââ
A0 = âxâ
CS = â1â
Dack = â0â
ââ
TC
#1
ââ
â
â
#0
3
req
#1
ââ ââ
(5)
ââ ââ
Memory address
Counter end
Burst end
010016
010116
010216
Acknowledgment of
internal memory access
ack
ack
<Initial setting>
External I/O configuration register
Memory channel operation mode register
Memory address counter
End address register
Set as necessary.
MC_DIR[1:0] (Memory channel direction control) = 012 (Receive mode)
Burst (burst) = â1â (Burst mode)
(Example) 010016
(Example) 010716
<Operation start command>
EXB interrupt source enable register
MC_ENB (Memory channel operation enable) = â1â (Operation start)
â When a rise of TC is detected, negation of the memory channel request which synchronized with a rise of Ï is made.
â When the write operation to the end address has been completed, the memory channel operation end interrupt is generated.
Fig. 96 Memory channel receiving operation (3)
â
â
5
â
Rev.3.00 Oct 05, 2006 page 67 of 129
REJ03B0192-0300
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