38K0 Datasheet, PDF (29/133 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

38K0 Group
USB Interrupt Function
USB Interrupt Control Circuit (USBINTCON) has 3 requests and
16 USB-device interrupt request sources. Each interrupt source
register enables the user to easily determine which interrupt has
occurred.
Table 7 shows the list of USB interrupt sources.
Table 7 USB interrupt sources
Interrupt request bit
USB interrupt bit
(IREQ1: Address 003C16) (USBIREQ: Address 001716)
USB bus reset
—
USB SOF
—
USB device
EP00
EP01
EP02
EP03
SUS
RSM
Interrupt source
At USB bus reset signal detection:
After enabling the USB module (USBE = “1”), an interrupt request occurs
when 2.5 µs SE0 state is detected in D0+/D0- port.
(Equivalent to 120-clock length when fUSB = 48 MHz)
At SOF packet receive:
After enabling the USB module (USBE = “1”), an interrupt request occurs
when SOF packet is detected in D0+/D0- port.
Its occurrence does not depend on frame-time or CRC value after SOF
packet is transferred.
(Normally, SOF packet detection occurs only when fUSB = 48 MHz)
At Endpoint 00 data transfer complete:
•Buffer ready (read/write enabled state)
•Control transfer completed
•Status stage transition
•SETUP buffer ready (read enabled state)
•Control transfer error
At Endpoint 01 data transfer complete:
•Buffer 0 ready (read/write enabled state)
•Buffer 1 ready (read/write enabled state)
•Transfer error
At Endpoint 02 data transfer complete:
•Buffer 0 ready (read/write enabled state)
•Buffer 1 ready (read/write enabled state)
•Transfer error
At Endpoint 03 data transfer complete:
•Buffer 0 ready (read/write enabled state)
•Buffer 1 ready (read/write enabled state)
•Transfer error
At suspend signal detection:
After enabling the USB module (USBE = “1”), an interrupt request occurs
when 3 ms J state is detected in D0+/D0- port.
(Equivalent to 144,000 clock-length when fUSB = 48MHz)
At resume signal detection:
After enabling the USB module (USBE = “1”) and resume interrupt (RSME
= “1”), an interrupt request occurs when a bus state change (J state to
SE0 or K state) is detected in D0- port.
Rev.3.00 Oct 05, 2006 page 29 of 129
REJ03B0192-0300