38K0 Datasheet, PDF (64/133 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

38K0 Group
(2) CPU Channel Transmitting Operation
CPU channel transmitting operation is shown bellow.
➀
Address ExA0
Chip select ExCS
Read ExRD
Write ExWR
Data DQ0 to DQ7
➁
➂
A0 = “1”
CS = “0”
➂
#0
➁’
A0 = “1”
CS = “0”
#1
Internal clock φ
Interrupt request ExINT
[TxB_RDY]
Transmit buffer empty bit
TXB_EMPTY
Receive buffer RXBUF
Transmit buffer TXBUF
➀
CPU channel transmit enable bit
TXB_ENB
Transmit data write
TxB_RDY
#0
➁
TxB_RDY
#1
➁’
<Initial setting>
External I/O configuration register
INT_CTR[3:1] (P33/ExINT pin control) = 0102 (TxB_RDY interrupt)
<Operation start>
EXB interrupt source enable register
TXB_ENB (CPU channel transmit enable) = “1” (Transmit buffer empty interrupt enabled)
➀ Writing the command for enabling operation generates TXB_EMPTY interrupt.
If the CPU channel transmit enable bit (TXB_ENB) is “0”, both the transmit buffer empty bit (TXB_EMPTY) and the transmit buffer ready signal (TxB_RDY) to
an external are inactive.
➁ When the CPU writes the data into the transmit buffer (TXBUF) with an interrupt processing program, the transmit buffer empty bit (TXB_EMPTY) is cleared
to “0” and assertion of the transmit buffer ready signal (TxB_RDY) to an external is made.
➂ When a read operation is performed from an external MCU bus in the condition of ExCS = “L” and ExA0 = “H”, it will result in as follows:
• The contents of the transmit buffer (TXBUF) is read out
• The transmit buffer empty bit (TXB_EMPTY) is set to “1”
• Negation of the transmit buffer ready signal (TxB_RDY) to an external is made.
Fig. 93 CPU channel tranmitting operation
Rev.3.00 Oct 05, 2006 page 64 of 129
REJ03B0192-0300