38K0 Datasheet, PDF (66/133 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

38K0 Group
(4) Memory Channel Receiving Operation (2)-
Burst Mode
Memory channel receiving operation (2) is shown bellow.
Address ExA0
Chip select ExCS
DMA acknowledge
ExDACK
Read ExRD
Write ExWR
Data DQ0 to DQ7
Internal clock φ
DMA request
ExDREQ
mWR detection
mWR detection
Receive buffer RXBUF
➀
➁
➂
➁’
➃
➄
A0 = “x”
A0 = “x”
A0 = “x”
CS = “1”
CS = “1”
CS = “1”
Dack = “0”
Dack = “0”
Dack = “0”
➁
➁’
#0
#1
#2
Mch_req
#0
#1
#2
Operation enabled
➀
Main sequencer
0
1
2
Memory channel operation
end interrupt
Internal memory access
3
req
req
5
req
Memory address
Counter end
Burst end
010016
010116
010216
010316
Acknowledgment of
internal memory access
ack
➂
ack
➃
ack
➄
<Initial setting>
External I/O configuration register
Memory channel operation mode register
Memory address counter
End address register
Set as necessary.
MC_DIR[1:0] (Memory channel direction control) = 012 (Receive mode)
Burst (burst) = “1” (Burst mode)
(Example) 010016
(Example) 010216
<Operation start command>
EXB interrupt source enable register
MC_ENB (Memory channel operation enable) = “1” (Operation start)
➀ In the memory channel receive mode when the command for enabling operation is written, assertion of the memory channel request which synchronized
with a rise of φ is made.
➁ When a rise of ExWR is detected, an internal memory access sequence which synchronized with a rise of φ is activated and a data is written in the internal
memory within two clocks at a minimum.
➂ The memory address counter is increased simultaneously at the former data write completion.
➃ When the memory address counter reaches the end address, the detection circuit of external write signal (ExWR) operation is enabled and negation of the
memory channel request which synchronized with the following φ is made.
➄ When the write operation to the end address has been completed, the memory address counter is increased and the memory channel operation end
interrupt is generated.
Fig. 95 Memory channel receiving operation (2)
Rev.3.00 Oct 05, 2006 page 66 of 129
REJ03B0192-0300