38K0 Datasheet, PDF (51/133 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

38K0 Group
EXTERNAL BUS INTERFACE (EXB)
The external bus interface (EXB) controls the data transfer be-
tween the external MCU and the 38K0 group’s CPU or its
memory (multichannel RAM). The external bus interface is shown
below.
CPU
CPU channel
[Interrupt type]
External bus interface
(EXB)
Memory channel
[Direct RAM access type]
38K0 group
Program ROM
Multichannel RAM
Peripheral functions
USB
USB bus
(USB host)
Fig. 73 External bus interface
qCPU channel
It is a data transfer course by the interrupt processing between the
external MCU and the 38K0 group’s CPU.
qMemory channel
It is a data transfer course by direct RAM access of the memory
channel controller between the external MCU and the 38K0
group’s memory (multichannel RAM)
qData transfer of memory channel
When the burst mode is selected with the burst bit of the memory
channel operation mode register, data transfer can be carried out
at the highest speed. After the external bus interface detects a rise
of external read signal/write signal and synchronizes it with the in-
ternal clock φ, it completes the data transfer between the transmit/
receive buffer and the multichannel RAM in two clocks.
However, the waiting time of two clocks at a maximum is gener-
ated to access the multichannel RAM in USB being operating
because the USB has priority to access.
Therefore, it is necessary to set up the access interval which fills
the following timing with the external MCU bus side.
In φ = 8 MHz, data transfer at about 2 Mbytes/second is possible
at a maximum. When there is access simultaneously from the
USB, it is about 1.3 Mbytes/second.
In φ = 6 MHz, data transfer at about 1.5 Mbytes/second is possible
at a maximum. When there is access simultaneously from the
USB, it is about 1 Mbytes/second.
Address
CS, RD, WR,
DMA acknowledge
Fig. 74 Data transfer timing of memory channel
Rev.3.00 Oct 05, 2006 page 51 of 129
REJ03B0192-0300
Access cycle time from externals:
•3 clocks or more of φ + Signal delay time + Data setup
time of external MCU in USB inactive
•5 clocks or more of φ + Signal delay time + Data setup
time of external MCU in USB active