38K0 Datasheet, PDF (74/133 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

38K0 Group
WATCHDOG TIMER
The watchdog timer gives a mean of returning to the reset status
when a program cannot run on a normal loop (for example, be-
cause of a software run-away). The watchdog timer consists of an
8-bit watchdog timer L and an 8-bit watchdog timer H.
Standard Operation of Watchdog Timer
When any data is not written into the watchdog timer control reg-
ister (address 003916) after resetting, the watchdog timer is in the
stop state. The watchdog timer starts to count down by writing an
optional value into the watchdog timer control register (address
003916) and an internal reset occurs at an underflow of the watch-
dog timer H.
Accordingly, programming is usually performed so that writing to
the watchdog timer control register (address 003916) may be
started before an underflow. When the watchdog timer control reg-
ister (address 003916) is read, the values of the high-order 6 bits
of the watchdog timer H, STP instruction disable bit (bit 6), and
watchdog timer H count source selection bit (bit 7) are read.
Initial Value of Watchdog Timer
At reset or writing to the watchdog timer control register (address
003916), each watchdog timer H and L is set to “FF16.”
qWatchdog timer H count source selection bit operation
Bit 7 of the watchdog timer control register (address 003916) per-
mits selecting a watchdog timer H count source. When this bit is
set to “0”, the count source becomes the underflow signal of
watchdog timer L. The detection time is set to 131.072 ms at sys-
tem clock 8 MHz frequency.
When this bit is set to “1”, the count source becomes the system
clock divided by 16. The detection time in this case is set to 512
µs at system clock 8 MHz frequency. This bit is cleared to “0” after
resetting.
qOperation of STP instruction disable bit
Bit 6 of the watchdog timer control register (address 003916) per-
mits disabling the STP instruction when the watchdog timer is in
operation.
When this bit is “0”, the STP instruction is enabled.
When this bit is “1”, the STP instruction is disabled.
Once the STP instruction is executed, an internal reset occurs.
When this bit is set to “1”, it cannot be rewritten to “0” by program.
This bit is cleared to “0” after resetting.
System clock
“FF16” is set when
watchdog timer
control register is
written to.
Watchdog timer L (8)
1/16
Data bus
“0”
“1”
Watchdog timer H (8)
Watchdog timer H count
source selection bit
“FF16” is set when
watchdog timer
control register is
written to.
STP instruction disable bit
STP instruction
RESET
Reset circuit
Internal reset
Fig. 105 Block diagram of Watchdog timer
b7
b0
Watchdog timer control register
(WDTCON : address 003916)
Watchdog timer H (for read-out of high-order 6 bit)
STP instruction disable bit
0: STP instruction enabled
1: STP instruction disabled
Fig. 106 Structure of Watchdog timer control register
Watchdog timer H count source selection bit
0: Watchdog timer L underflow
1: System clock/16
Rev.3.00 Oct 05, 2006 page 74 of 129
REJ03B0192-0300