38K0 Datasheet, PDF (69/133 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

38K0 Group
(7) Memory Channel Transmitting Operation
(2)-Burst Mode
Memory channel transmitting operation (2) is shown bellow.
➀
➁
➂
➃
➂’
➄
➅
Address ExA0
Chip select ExCS
DMA acknowledge
ExDACK
Read ExRD
Write ExWR
A0 = “x”
CS = “1”
Dack = “0”
➂
A0 = “x”
CS = “1”
Dack = “0”
➂’
A0 = “x”
CS = “1”
Dack = “0”
➅
Data DQ0 to DQ7
#0
#1
#2
Internal clock φ
DMA request
ExDREQ
mRD detection
Mch_req
mRD detection
Transmission completed
Transmit buffer TXBUF
#0
Operation enabled
Main sequencer
Memory channel operation
end interrupt
Internal memory access
➀
0
1
2
req
#1
#2
3
req
4
5
req
Memory address
Counter end
Burst end
010016
010116
010216
010316
Acknowledgment of
internal memory access
ack
➁
ack
➃
ack
➄
<Initial setting>
External I/O configuration register
Memory channel operation mode register
Memory address counter
End address register
Set as necessary.
MC_DIR[1:0] (Memory channel direction control) = 102 (Transmit mode)
Burst (burst) = “1” (Burst mode)
(Example) 010016
(Example) 010216
<Operation start command>
EXB interrupt source enable register
MC_ENB (Memory channel operation enable) = “1” (Operation start)
➀ In the memory channel transmit mode when the command for enabling operation is written, an internal memory access sequence which synchronized with
a rise of φ is activated.
➁ A data is read out from the internal memory within two clocks at a minimum and this data is stored in the transmit buffer (TXBUF). The memory address
counter is simultaneously increased and assertion of the memory channel request is made.
➂ When a rise of ExRD is detected, an internal memory access sequence which synchronized with a rise of φ is activated.
➃ A data is read out from the internal memory within two clocks at a minimum and this data is stored in the transmit buffer (TXBUF). The memory address
counter is simultaneously increased.
➄ When the read operation from the end address has been completed, the detection circuit of external read signal (ExRD) operation is enabled and negation
of the memory channel request which synchronized with the following φ is made.
➅ When a rise of ExRD is detected, the memory channel operation sequence ends and the memory channel operation end interrupt is generated.
Fig. 98 Memory channel tranmitting operation (2)
Rev.3.00 Oct 05, 2006 page 69 of 129
REJ03B0192-0300