38K0 Datasheet, PDF (22/133 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

38K0 Group
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by
setting the serial I/O mode selection bit of the serial I/O control
register to “0”.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer regis-
ter, but the two buffers have the same address in memory. Since
the shift register cannot be written to or read from directly, transmit
data is written to the transmit buffer, and receive data is read from
the receive buffer.
The transmit buffer can also hold the next data to be transmitted,
and the receive buffer register can hold a character while the next
character is being received.
P40/EXDREQ/RxD
P42/EXTC/SCLK
Data bus
Address 002616
Serial I/O1 control register Address 0FE016
OE
Receive buffer register
Character length selection bit
STdetector 7 bits
Receive shift register
8 bits
Receive buffer full flag (RBF)
Receive interrupt request (RI)
1/16
PE FE SP detector
Clock control circuit
UART control register
Address 0FE116
Serial I/O synchronous clock selection bit
System clock
P41/EXDACK/TxD
BRG count source selection bit ^{Frequency division ratio 1/(n+1)}
Baud rate generator
1/4
Address 0FE216
ST/SP/PA generator
1/16
Transmit shift register shift completion flag (TSC)
Transmit shift register
Transmit interrupt source selection bit
Transmit interrupt request (TI)
Character length selection bit
Transmit buffer register
Address 002616
Transmit buffer empty flag (TBE)
Serial I/O status register Address 002716
Data bus
Fig. 20 Block diagram of UART serial I/O
Transmit or receive clock
Transmit buffer write signal
Serial output TXD
Receive buffer read signal
TBE=0
TSC=0
TBE=1
ST
TBE=0
D0
D1
1 start bit
7 or 8 data bits
1 or 0 parity bit
1 or 2 stop bit (s)
Serial input RXD
ST
D0
D1
TBE=1
SP
ST D0
TSC=1^✽
D1
SP
✽ _{Generated at 2nd bit in 2-stop-bit mode}
RBF=1
SP ST
RBF=0
D0
D1
RBF=1
SP
Notes 1 : Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
2 : The transmit interrupt (TI) can be generated to occur when either the TBE or TSC flag becomes “1”, depending on the setting of the transmit interrupt
source selection bit (TIC) of the serial I/O1 control register.
3 : The receive interrupt (RI) is set when the RBF flag becomes “1”.
4 : After data is written to the transmit buffer register when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.
Fig. 21 Operation of UART serial I/O function
Rev.3.00 Oct 05, 2006 page 22 of 129
REJ03B0192-0300