RX220_15 Datasheet, PDF (8/107 Pages) Renesas Technology Corp – Renesas MCUs

RX220 Group
1.3 Block Diagram
Figure 1.2 shows a block diagram.
1. Overview
ROM
RAM
RX CPU
Clock
generation
circuit
ICUb
DTCa
DMACA × 4
channels
E2 DataFlash
IWDTa
ELC
CRC
SCIe × 4 channels
(including one channel for IrDA)
SCIf × 1 channel
RSPI × 1 channel
RIIC × 1 channel
MTU2a × 6 channels
POE2a
TMR × 2 channels (unit 0)
TMR × 2 channels (unit 1)
CMT × 2 channels (unit 0)
CMT × 2 channels (unit 1)
RTCc
12-bit A/D converter × 16 channels
DOC
Comparator A × 2 channels
CAC
BSC
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port A
Port B
Port C
Port D
Port E
Port H
Port J
ICUb:
Interrupt controller
DTCa: Data transfer controller
DMACA: DMA controller
BSC:
Bus controller
IWDTa: Independent watchdog timer
ELC:
Event link controller
CRC:
CRC (cyclic redundancy check) calculator
SCIe, SCIf: Serial communications interface
IrDA:
Infrared Data Association
Figure 1.2
Block Diagram
RSPI: Serial peripheral interface
RIIC: I²C bus interface
MTU2a: Multi-function timer pulse unit 2
POE2a: Port output enable 2
TMR: 8-bit timer
CMT: Compare match timer
RTCc: Realtime clock
DOC: Data operation circuit
CAC: Clock-frequency accuracy measuring circuit
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
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