RX220_15 Datasheet, PDF (2/107 Pages) Renesas Technology Corp – Renesas MCUs

RX220 Group
1. Overview
1. Overview
1.1 Outline of Specifications
Table 1.1 lists the specifications in outline, and Table 1.2 gives a comparison of the functions of products in different
packages.
Table 1.1 is for products with the greatest number of functions, so numbers of peripheral modules and channels will
differ in accord with the package. For details, see Table 1.2, Comparison of Functions for Different Packages.
Table 1.1
Outline of Specifications (1 / 3)
Classification
CPU
Module/Function
CPU
Memory
ROM
RAM
E2 DataFlash
MCU operating mode
Clock
Clock generation circuit
Reset
Voltage detection Voltage detection circuit
(LVDAa)
Low power
consumption
Interrupt
Low power consumption
facilities
Function for lower
operating power
consumption
Interrupt controller (ICUb)
Description
 Maximum operating frequency: 32 MHz
 32-bit RX CPU
 Minimum instruction execution time: One instruction per state (cycle of the system clock)
 Address space: 4-Gbyte linear
 Register
General purpose: Sixteen 32-bit registers
Control: Eight 32-bit registers
Accumulator: One 64-bit register
 Basic instructions: 73
 DSP instructions: 9
 Addressing modes: 10
 Data arrangement
Instructions: Little endian
Data: Selectable as little endian or big endian
 On-chip 32-bit multiplier: 32  32  64 bits
 On-chip divider: 32 / 32  32 bits
 Barrel shifter: 32 bits
 Capacity: 32 K/64 K/128 K/256 Kbytes
 32 MHz, no-wait memory access
 On-board programming: 3 types
 Capacity: 4 K/8 K/16 Kbytes
 32 MHz, no-wait memory access
E2 DataFlash capacity: 8 Kbytes
Single-chip mode
 Main clock oscillator, sub-clock oscillator, low-speed on-chip oscillator, high-speed on-chip oscillator,
and IWDT-dedicated on-chip oscillator
 Oscillation stop detection
 Measuring circuit for accuracy of clock frequency (clock-accuracy check: CAC)
 Independent settings for the system clock (ICLK), peripheral module clock (PCLK), and flashIF clock
(FCLK)
The CPU and system sections such as other bus masters run in synchronization with the system
clock (ICLK): 32 MHz (at max.)
Peripheral modules run in synchronization with the peripheral module clock (PCLK): 32 MHz (at
max.)
The flash peripheral circuit runs in synchronization with the flash peripheral clock (FCLK): 32 MHz (at
max.)
RES# pin reset, power-on reset, voltage monitoring reset, independent watchdog timer reset, and
software reset
 When the voltage on VCC falls below the voltage detection level, an internal reset or internal interrupt
is generated.
Voltage detection circuit 0 is capable of selecting the detection voltage from 4 levels
Voltage detection circuit 1 is capable of selecting the detection voltage from 16 levels
Voltage detection circuit 2 is capable of selecting the detection voltage from 16 levels
 Module stop function
 Three low power consumption modes
Sleep mode, all-module clock stop mode, and software standby mode
 Four operating power control modes
Middle-speed operating mode 1A, middle-speed operating mode 1B, low-speed operating mode 1,
low-speed operating mode 2
 Interrupt vectors: 106
 External interrupts: 9 (NMI, IRQ0 to IRQ7 pins)
 Non-maskable interrupts: 5 (the NMI pin, oscillation stop detection interrupt, voltage monitoring 1
interrupt, voltage monitoring 2 interrupt, and IWDT interrupt)
 16 levels specifiable for the order of priority
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
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