RX220_15 Datasheet, PDF (3/107 Pages) Renesas Technology Corp – Renesas MCUs

RX220 Group
1. Overview
Table 1.1
Outline of Specifications (2 / 3)
Classification
DMA
Module/Function
DMA controller (DMACA)
I/O ports
Data transfer controller
(DTCa)
General I/O ports
Event link controller (ELC)
Multi-function pin controller (MPC)
Timers
Multi-function timer pulse
unit 2 (MTU2a)
Port output enable 2
(POE2a)
8-bit timer (TMR)
Compare match timer
(CMT)
Independent watchdog
timer (IWDTa)
Realtime clock (RTCc)
Description
 4 channels
 Three transfer modes: Normal transfer, repeat transfer, and block transfer
 Activation sources: Software trigger, external interrupts, and interrupt requests from peripheral
functions
 Three transfer modes: Normal transfer, repeat transfer, and block transfer
 Activation sources: Interrupts
 Chain transfer function
100-pin/64-pin/48-pin
 I/O pin: 84/48/34
 Input: 1/1/1
 Pull-up resistors: 84/48/34
 Open-drain outputs: 35/26/20
 5-V tolerance: 4/2/2
 8-bit port switching function: Not supported/supported/supported
 Event signals of 46 types can be directly connected to the module
 Operations of timer modules are selectable at event input
 Capable of event link operation for port B
 Capable of selecting input/output function from multiple pins
 (16 bits  6 channels)  1 unit
 Time bases for the six 16-bit timer channels can be provided via up to 16 pulse-input/output lines and
three pulse-input lines
 Select from among eight or seven counter-input clock signals for each channel (PCLK/1, PCLK/4,
PCLK/16, PCLK/64, PCLK/256, PCLK/1024, MTCLKA, MTCLKB, MTCLKC, MTCLKD) other than
channel 5, for which only four signals are available.
 Input capture function
 21 output compare/input capture registers
 Pulse output mode
 Complementary PWM output mode
 Reset synchronous PWM mode
 Phase-counting mode
 Generation of triggers for A/D converter conversion
Controls the high-impedance state of the MTU’s waveform output pins
 (8 bits  2 channels)  2 units
 Select from among seven internal clock signals (PCLK/1, PCLK/2, PCLK/8, PCLK/32, PCLK/64,
PCLK/1024, PCLK/8192) and one external clock signal
 Capable of output of pulse trains with desired duty cycles or of PWM signals
 The 2 channels of each unit can be cascaded to create a 16-bit timer
 Capable of generating baud-rate clocks for SCI5, SCI6, and SCI12
 (16 bits  2 channels)  2 units
 Select from among four clock signals (PCLK/8, PCLK/32, PCLK/128, PCLK/512)
 14 bits  1 channel
 Counter-input clock: IWDT-dedicated on-chip oscillator
Frequency divided by 1, 16, 32, 64, 128, or 256
 Clock source: Sub-clock
 Time count or 32-bit binary count in second units basis selectable
 Time/calendar
 Interrupt sources: Alarm interrupt, periodic interrupt, and carry interrupt
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
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