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RX220_15 Datasheet, PDF (76/107 Pages) Renesas Technology Corp – Renesas MCUs
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RX220 Group
5. Electrical Characteristics
Table 5.29 Timing of On-Chip Peripheral Modules (4)
Conditions: VCC = AVCC0 = 2.7 to 5.5 V, VSS = AVSS0 = VREFL0 = 0 V, fPCLKB = up to 32 MHz, Ta = –40 to +105°C
Item
Symbol
Min.*1,*2
Max.
Unit
Test
Conditions
RIIC
(Standard
mode, SMBus)
RIIC
(Fast mode)
SCL input cycle time
SCL input high pulse width
SCL input low pulse width
SCL, SDA input rise time
SCL, SDA input fall time
SCL, SDA input spike pulse removal time
SDA input bus free time
Start condition input hold time
Restart condition input setup time
Stop condition input setup time
Data input setup time
Data input hold time
SCL, SDA capacitive load
SCL input cycle time
SCL input high pulse width
SCL input low pulse width
SCL, SDA input rise time
SCL, SDA input fall time
SCL, SDA input spike pulse removal time
SDA input bus free time
Start condition input hold time
Restart condition input setup time
Stop condition input setup time
Data input setup time
Data input hold time
SCL, SDA capacitive load
tSCL
tSCLH
tSCLL
tSr
tSf
tSP
tBUF
tSTAH
tSTAS
tSTOS
tSDAS
tSDAH
Cb
tSCL
tSCLH
tSCLL
tSr
tSf
tSP
tBUF
tSTAH
tSTAS
tSTOS
tSDAS
tSDAH
Cb
6 (12) × tIICcyc + 1300
3 (6) × tIICcyc + 300
3 (6) × tIICcyc + 300
—
—
—
—
1000
ns Figure 5.48
ns
ns
ns
—
300
ns
0
3 (6) × tIICcyc + 300
tIICcyc + 300
1000
1 (5) × tIICcyc ns
—
ns
—
ns
—
ns
1000
—
ns
tIICcyc + 50
0
—
ns
—
ns
—
400
pF
6 (12) × tIICcyc + 600
3 (6) × tIICcyc + 300
3 (6) × tIICcyc + 300
20 + 0.1Cb
20 + 0.1Cb
0
3 (6) × tIICcyc + 300
tIICcyc + 300
300
—
ns Figure 5.48
—
ns
—
ns
300
ns
300
ns
1 (4) × tIICcyc ns
—
ns
—
ns
—
ns
300
—
ns
tIICcyc + 50
0
—
ns
—
ns
—
400
pF
Note: • tIICcyc: RIIC internal reference count clock (IICφ) cycle
Note 1. The value in parentheses is used when ICMR3.NF[1:0] are set to 11b while a digital filter is enabled with ICFER.NFE = 1.
Note 2. Cb indicates the total capacity of the bus line.
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 76 of 105
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