RX220_15 Datasheet, PDF (73/107 Pages) Renesas Technology Corp – Renesas MCUs

RX220 Group
5. Electrical Characteristics
5.3.5
Timing of On-Chip Peripheral Modules
Table 5.26 Timing of On-Chip Peripheral Modules (1)
Conditions: VCC = AVCC0 = 1.62 to 5.5 V, VSS = AVSS0 = VREFL0 = 0 V, T_a = –40 to +105°C
Item
Symbol
Min.
Max.
I/O ports Input data pulse width
t_PRW
1.5
—
MTU
Input capture input pulse width
Single-edge setting
t_TICW
1.5
—
Both-edge setting
2.5
—
Timer clock pulse width
Single-edge setting t_TCKWH,
1.5
—
Both-edge setting
t_TCKWL
2.5
—
Phase counting
mode
2.5
—
POE
8-bit
timer
POE# input pulse width
Timer clock pulse width
t_POEW
1.5
—
Single-edge setting t_TMCWH,
1.5
—
Both-edge setting
t_TMCWL
2.5
—
SCI
Input clock cycle
Asynchronous
t_Scyc
4
—
Clock synchronous
6
—
Input clock pulse width
Input clock rise time
Input clock fall time
Output clock cycle*²
t_SCKW
0.4
0.6
t_SCKr
—
20
t_SCKf
—
20
Asynchronous
t_Scyc
16
—
Clock synchronous
4
—
Output clock pulse width*²
t_SCKW
0.4
0.6
Output clock rise time*²
t_SCKr
—
20
Output clock fall time*²
t_SCKf
—
20
Transmit data delay
Clock
2.7 V ≤ VCC ≤ 5.5 V
t_TXD
—
40
time*³
synchronous _{1.62 V ≤ VCC < 2.7 V}
—
80
Receive data setup time Clock
2.7 V ≤ VCC ≤ 5.5 V
t_RXS
40
—
synchronous _{1.62 V ≤ VCC < 2.7 V}
80
—
Receive data hold time
A/D
Trigger input pulse width
converter
CAC
CACREF input pulse width
Clock synchronous
t_RXH
40
—
t_TRGW
1.5
—
t_Pcyc ≤ t_cac*⁴
t_Pcyc > t_cac*⁴
t_CACREF 4.5 t_cac + 3 t_Pcyc
—
5 t_cac + 6.5 t_Pcyc
Note 1. t_Pcyc: PCLKB cycle
Note 2. Value when the drive capacity of clock output ports is set to normal output.
Note 3. Value when the drive capacity of data output ports is set to normal output.
Note 4. t_cac: CAC count clock source cycle
Unit*¹
t_Pcyc
t_Pcyc
Test
Conditions
Figure 5.33
Figure 5.34
t_Pcyc Figure 5.35
t_Pcyc
t_Pcyc
Figure 5.36
Figure 5.37
t_Pcyc Figure 5.38
t_Scyc
ns
ns
t_Pcyc
C = 30 pF
Figure 5.39
t_Scyc
ns
ns
ns
ns
ns
t_Pcyc
Figure 5.40
ns
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 73 of 105