RX220_15 Datasheet, PDF (75/107 Pages) Renesas Technology Corp – Renesas MCUs

RX220 Group
5. Electrical Characteristics
Table 5.28 Timing of On-Chip Peripheral Modules (3)
Conditions: VCC = AVCC0 = 1.62 to 5.5 V, VSS = AVSS0 = VREFL0 = 0 V, T_a = –40 to +105°C
Item
Symbol
Min.
Max.
Simple SCK clock cycle output (master)*²
SPI
SCK clock cycle input (slave)
t_SPcyc
4
65536
6
65536
SCK clock high pulse width*²
t_SPCKWH
0.4
0.6
SCK clock low pulse width*²
t_SPCKWL
0.4
0.6
SCK clock rise/fall time
t_SPCKr, t_SPCKf
—
20
Data input setup time
2.7 V ≤ VCC ≤ 5.5 V
t_SU
40
—
1.62 V ≤ VCC < 2.7 V
80
—
Data input hold time
SS input setup time
SS input hold time
Data output delay time
2.7 V ≤ VCC ≤ 5.5 V
1.62 V ≤ VCC < 2.7 V
t_H
t_LEAD
t_LAG
t_OD
40
—
6
—
6
—
—
40
—
80
Data output hold time
Data rise/fall time
SS input rise/fall time
Slave access time
Slave output release time
t_OH
0
—
t_Dr, t_Df
—
20
t_SSLr, t_SSLf
—
20
t_SA
—
5
t_REL
—
5
Note 1. t_Pcyc: PCLKB cycle
Note 2. Value when the drive capacity of clock output ports is set to normal output.
Unit*¹
t_Pcyc
Test Conditions
C = 30 pF
Figure 5.41
t_SPcyc
t_SPcyc
ns
ns
ns
t_Pcyc
t_Pcyc
ns
C = 30 pF
Figure 5.42 to
Figure 5.47
ns
ns
ns
t_Pcyc
t_Pcyc
C = 30 pF
Figure 5.45
and
Figure 5.47
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
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