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RX220_15 Datasheet, PDF (74/107 Pages) Renesas Technology Corp – Renesas MCUs
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RX220 Group
5. Electrical Characteristics
Table 5.27 Timing of On-Chip Peripheral Modules (2)
Conditions: VCC = AVCC0 = 1.62 to 5.5 V, VSS = AVSS0 = VREFL0 = 0 V, Ta = –40 to +105°C
Item
Symbol
Min.
Max.
RSPI
RSPCK clock cycle*2 Master
Slave
RSPCK clock high Master
pulse width*2
Slave
RSPCK clock low
pulse width*2
Master
Slave
RSPCK clock rise/fall Output
time*2
Input
Data input setup time Master
Slave
Data input hold time Master
SSL setup time
SSL hold time
Data output delay
time
Slave
Master
Slave
Master
Slave
Master
Slave
Data output hold time Master
Slave
Successive
transmission delay
time
Master
Slave
MOSI and MISO rise/ Output
fall time
Input
SSL rise/fall time
Output
Input
Slave access time
Slave output release time
tSPcyc
tSPCKWH
tSPCKWL
2.7 V ≤ VCC ≤ 5.5 V
1.62 V ≤ VCC < 2.7 V
tSPCKr,
tSPCKf
tSU
PCLKB set to a
division ratio other
than divided by 2
PCLKB set to
divided by 2
tH
tHF
tH
tLEAD
tLAG
2.7 V ≤ VCC ≤ 5.5 V
tOD
1.62 V ≤ VCC < 2.7 V
2.7 V ≤ VCC ≤ 5.5 V
1.62 V ≤ VCC < 2.7 V
tOH
tTD
2.7 V ≤ VCC ≤ 5.5 V
1.62 V ≤ VCC < 2.7 V
tDr, tDf
tSSLr,
tSSLf
tSA
tREL
2
8
(tSPcyc – tSPCKr –
tSPCKf)/2 – 3
(tSPcyc – tSPCKr –
tSPCKf)/2
(tSPcyc – tSPCKr –
tSPCKf)/2 – 3
(tSPcyc – tSPCKr –
tSPCKf)/2
—
—
—
4
20 – tPcyc
tPcyc
0
20 + 2 × tPcyc
1
4
1
4
—
—
—
—
0
0
tSPcyc + 2 × tPcyc
4 × tPcyc
—
—
—
—
—
—
—
4096
4096
—
—
—
—
10
20
1
—
—
—
—
—
8
—
8
—
14
28
3 × tPcyc + 40
3 × tPcyc + 80
—
—
8 × tSPcyc + 2 ×
tPcyc
—
10
20
1
20
1
4
3
Unit*1
Test
Conditions
tPcyc C = 30 pF
Figure 5.41
ns
ns
ns
μs
ns C = 30 pF
Figure 5.42
to
ns Figure 5.47
tSPcyc
tPcyc
tSPcyc
tPcyc
ns
ns
ns
ns
μs
ns
μs
tPcyc
tPcyc
C = 30 pF
Figure 5.45
and
Figure 5.47
Note 1. tPcyc: PCLKB cycle
Note 2. Value when the drive capacity of clock output ports is set to normal output.
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 74 of 105
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