PD72042B_15 Datasheet, PDF (8/92 Pages) Renesas Technology Corp – LSI DEVICE FOR Inter Equipment BusTM (IEBusTM) PROTOCOL CONTROL

µPD72042B
1. PIN FUNCTIONS
1.1 PIN FUNCTIONS
Pin No. Pin^Note
I/O^Note
1
SCK
Input
2
SI (SIO) Input (I/O)
3
SO (NC) Output
(none)
Function
I/O format^Note
Serial clock input pin for CPU interface
Serial data pin for CPU interface. (This pin
functions as an input pin when 3-wire serial
I/O mode is selected, or as an I/O pin when
2-wire serial I/O mode is selected.)
CMOS input
CMOS input
(CMOS I/O)
Serial data output pin for CPU interface. (The
pin functions as an output when 3-wire serial I/O
mode is selected. When 2-wire serial I/O mode
is selected, the pin is left open.)
CMOS output
(none)
When reset
[for both hardware
and software]
Input
Input
High-impedance
4
IRQ
Output
5
C/D
Input
6
XI
–
7
XO
8
GND
–
9
BUS–
I/O
10
BUS+
11
AVDD
–
12
SEL
Input
13
CS
Input
Output pin for making an interrupt request to the
CPU. When a return code or a program crash is
detected, a high-level signal is output on this pin
for at least 8 µs.
Input pin used to select control mode or data
read/write mode. When this pin is driven high,
internal register address setting and data read/
write are enabled. When the mode changes, the
serial clock counter is reset.
CMOS output
CMOS input
Pins for connecting a system clock resonator. A _–
6- or 6.29-MHz crystal or ceramic resonator
must be used. The accuracy of the frequency is
as follows;
Mode 0, 1: ±1.5%
Ground pin
–
I/O pins connected to the IEBus bus
–
Low level
Input
When reset by
hardware (Oscil-
lation stopped)
XI = GND
XO = High level
When reset by
software (Oscil-
lation continued)
–
High-impedance
Main power supply pin for the IEBus bus driver/ _–
receiver. When used, this pin must be tied to
VDD.
Input pin used to select either 3- or 2-wire serial
I/O mode. A high-level signal on this pin selects
3-wire serial I/O mode. A low-level signal on this
pin selects 2-wire serial I/O mode.
CMOS input
Chip select pin. When this pin is driven low, the
serial interface is enabled. When this pin is
driven high, the SO pin becomes high-imped-
ance, and the serial clock counter is reset.
CMOS input
–
Input
Input
Note Parentheses indicate the state corresponding to two-wire serial I/O mode.
6
Data Sheet S13990EJ3V0DS