PD72042B_15 Datasheet, PDF (26/92 Pages) Renesas Technology Corp – LSI DEVICE FOR Inter Equipment BusTM (IEBusTM) PROTOCOL CONTROL

µPD72042B
(2) Data read mode
When the C/D pin is set low after register read is selected in control mode, the data read mode is set. In data
read mode, the data in a read register is read on the SO pin upon detecting the falling edge of the SCK pin.
C/D
SCK
SI
× × × 1 A0 A1 A2 A3
SO
“1”
State
Control mode
(selection of register read)
Serial clock counter
reset pointer
D0 D1 D2 D3 D4 D5 D6 D7
Data read mode
Caution When the C/D pin is set high in data read mode, the serial clock counter is reset. Therefore, the
remaining bits of the byte cannot be read; at the next falling edge, read is performed starting from
the next byte in the case of RBF, or from the first bit for other registers.
(3) Data write mode
When the C/D pin is set low after register write has been selected in control mode, data write mode is set. In
data write mode, data for a write register is applied to the SI pin at the rising edge of the SCK pin.
C/D
SCK
SI
× × × 0 A0 A1 A2 A3
SO
State
Serial clock counter
reset pointer
“1”
Control mode
(selection of register write)
D0 D1 D2 D3 D4 D5 D6 D7
Data write mode
Caution Register overwrite is started immediately after the eighth clock rising edge. All registers other
than TBF are overwritten on the eighth clock rising edge. (Data of less than eight clock periods
is ignored.)
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Data Sheet S13990EJ3V0DS