PD72042B_15 Datasheet, PDF (46/92 Pages) Renesas Technology Corp – LSI DEVICE FOR Inter Equipment BusTM (IEBusTM) PROTOCOL CONTROL

µPD72042B
DAR1
DAR2
Broadcast address register
Address : 0110B (6H) (DAR1) High-order 4 bits
0111B (7H) (DAR2)
Read/write : Read
When reset : Undefined
The DAR1 and DAR2 registers are used to hold a broadcast address (master address) involved when a broadcast
reception error occurs.
DAR1 and DAR2 are updated each time a broadcast reception error occurs (SLRC of the RCR register is set to
1100). So, ensure that when a broadcast reception error occurs, the contents of DAR1 and DAR2 are read by the
microcomputer within the time indicated below.
b7
b4
b3
Broadcast address (low-order 4 bits)
—
b0
DAR1
b7
b0
Broadcast address (high-order 8 bits)
DAR2
• Maximum allowable DAR1 and DAR2 read time (t: At fX = 6 MHz):
Approx. 5420 µs (mode 0)
t
Approx. 1490 µs (mode 1)
IRQ
Cautions 1. If the microcomputer cannot read the data in DAR1 and DAR2 within the times indicated above,
DAR1 and DAR2 may be updated by the occurrence of another broadcast reception error, and
the subsequently updated broadcast address may be read.
2. A broadcast address is stored in DAR1 and DAR2 when DERC (broadcast reception selection)
of the CMR register is set to 1.
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Data Sheet S13990EJ3V0DS