PD72042B_15 Datasheet, PDF (27/92 Pages) Renesas Technology Corp – LSI DEVICE FOR Inter Equipment BusTM (IEBusTM) PROTOCOL CONTROL

µPD72042B
3.2.2 Two-Wire Data Transfer (SEL = 0)
(1) Control mode
When the C/D input is set high, control mode is set to control data transfer. Data transfer control involves the
following processing.
1 Register address setting
2 Register read/write selection
C/D
SCK
SIO
R
× × × / A0 A1 A2 A3
W
Remark After reset (RESET) cancellation, the state enabling writing to the register at address 0000B is set.
Caution In control mode, each data item is read every eighth clock pulse. (Data of less than eight clock
periods is ignored.)
(2) Data read mode
C/D
SCK
SIO^Note
× × × 1 A0 A1 A2 A3
State
Serial clock counter
reset pointer
Control mode
(selection of register read)
D0 D1 D2 D3 D4 D5 D6 D7
Data read mode
Note
SIO pin input state
SIO pin output state
Cautions 1. When the C/D pin is set high in data read mode, the serial clock counter is reset. Therefore,
the remaining bits of the byte cannot be read; at the next falling edge, a read operation is
performed starting from the next byte in the case of RBF, or from the first bit for other registers.
2. The SIO pin is a CMOS I/O pin. So, be careful to avoid an output collision between the SIO
pin and the microcomputer. Further, a pull-up resistor is required when N-ch open-drain
output of the microcomputer is used. Note that if the last output level is low upon the
termination of read mode, current will flow constantly.
Data Sheet S13990EJ3V0DS
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