PD72042B_15 Datasheet, PDF (29/92 Pages) Renesas Technology Corp – LSI DEVICE FOR Inter Equipment BusTM (IEBusTM) PROTOCOL CONTROL

µPD72042B
3.3 CONNECTION TO A MICROCOMPUTER
(1) Three-wire serial I/O
120 Ω
5V
VDD
AVDD
180 Ω
TEST
BUS+
180 Ω
BUS–
6 MHz
XI
XO
GND
SEL
CS^{Note 1}
C/D
SCK
SI
SO
IRQ^{Note 2}
RESET
µ PD72042B
120 Ω
Microcomputer
5V
Low
voltage
detection
circuit
Output port
Output port
SCK
SO
SI
INT
75XL series
78K series
(2) Two-wire serial I/O
120 Ω
5V
VDD
AVDD
180 Ω
TEST
BUS+
180 Ω
BUS–
6 MHz
XI
XO
GND
SEL
CS^{Note 1}
C/D
SCK
SIO
SO
IRQ^{Note 2}
RESET
120 Ω
µ PD72042B
Microcomputer
Note 3
5V
Low
voltage
detection
circuit
Output port
Output port
SCK
SIO
INT
75XL series
78K series
Notes 1. When only the µPD72042B is to be controlled from a microcomputer via a serial I/O interface, the CS
pin must be tied low (by connecting it to GND).
2. When an interrupt is detected by polling (in FLG register read), IRQ may be left open. When high-volume
or high-speed data transfer is required, however, the system described above is recommended to ensure
reliable data transfer.
3. Required when the microcomputer’s N-ch open-drain output is used. The SIO pin of the µPD72042B
is a CMOS I/O pin.
Data Sheet S13990EJ3V0DS
27