PD72042B_15 Datasheet, PDF (18/92 Pages) Renesas Technology Corp – LSI DEVICE FOR Inter Equipment BusTM (IEBusTM) PROTOCOL CONTROL

µPD72042B
(7) Parity bit
A parity bit is used to check for errors in the transmission data.
A parity bit is added to the master address bits, slave address bits, control bits, data-length bits, and data bits.
Even parity is used. If the number of 1’s in the data is odd, the parity bit is set to 1. If the number of 1’s in the
data is even, the parity bit is set to 0.
(8) Acknowledge bit
In ordinary communication (one-unit-to-one-unit communication), an acknowledge bit is added in the following
positions to confirm that data has been received correctly:
• At the end of the slave address field
• At the end of the control field
• At the end of the data-length field
• At the end of the data field
The acknowledge bit is defined as follows:
• 0: Indicates that transmission data has been recognized. (ACK)
• 1: Indicates that no transmission data has been recognized. (NAK)
For broadcast, the acknowledge bit is ignored.
1 Acknowledge bit at the end of the slave address field
If any of the following is detected, the acknowledge bit at the end of the slave address field is set to NAK,
and transmission is stopped:
• The parity of the master address bits or slave address bits is incorrect.
• A timing error occurred (bit format error).
• No slave unit is found.
2 Acknowledge bit at the end of the control field
If any of the following is detected, the acknowledge bit at the end of the control field is set to NAK, and
transmission is stopped:
• The parity of the control bits is incorrect.
• Although the slave reception buffer^Note is not empty, bit 3 of the control bits is 1 (write operation).
• Although the slave transmission buffer^Note is empty, the control bits indicate data read (3H, 7H).
• For a locked unit, a unit other than the unit that specified the lock makes a request by using control bits
indicating 3H, 6H, 7H, AH, BH, EH, or FH.
• Although no lock has been set, control bits indicating lock address read (4H) are set.
• A timing error occurred.
• An undefined control bit setting has been made.
Note See (1) in Section 2.4.
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Data Sheet S13990EJ3V0DS