R8CL35A Datasheet, PDF (671/848 Pages) Renesas Technology Corp – RENESAS MCU R8C FAMILY / R8C/Lx SERIES

Under development ^{Preliminary specification}
Specifications in this manual are tentative and subject to change.
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
29. Hardware LIN
Timer RA Set to pulse width measurement mode
(1)
Bits TMOD2 to TMOD0 in TRAMR register←011b
Timer RA Set the pulse width measurement level to low
(1)
TEDGSEL bit in TRAIOC register ← 0
Timer RA Assign the TRAIO pin to P11_4
(1)
Bits TRAIOSEL1 to TRAIOSEL0 in TRASR register ← 10b
UART0 Assign the RXD0 pin to P11_4
Bits RXD0SEL1 to RXD0SEL0 in U0SR register ← 10b
INT1
Assign the INT1 pin to P11_4
INT4SEL0 bit in INTSR register ← 1
Set the TIOSEL bit in the
TRAIOC register to 1 to select the
hardware LIN function.
If the wake-up function is not
necessary, the setting of the INT4
pin can be omitted.
Timer RA Set the count source (f1, f2, f8, fOCO)
Bits TCK0 to TCK2 in TRAMR register
Timer RA Set the Synch Break width
TRAPRE register
TRA register
Hardware LIN Set the LIN operation to stop
LINE bit in LINCR register ← 0
Hardware LIN Set to slave mode
MST bit in LINCR register ← 0
(1)
Set the count source and registers
TRA and TRAPRE as appropriate
(1) _{for the Synch Break period.}
(1)
(1)
Hardware LIN Set the LIN operation to start
(1)
LINE bit in LINCR register ← 1
Hardware LIN Set the RXD0 input unmasking timing
(1)
(After Synch Break detection, or after Synch Field
measurement)
SBE bit in LINCR register
Hardware LIN
Set interrupts to enable
(1)
(Bus collision detection, Synch Break detection, Synch
Field measurement)
Bits BCIE, SBIE, SFIE in LINCR register
Select the timing at which to
unmask the RXD0 input for UART0.
If the RXD0 input is chosen to be
unmasked after Synch Break
detection, the Synch Field signal is
also input to UART0.
A
Note:
1. When the previous communication completes normally and header field reception is
performed again with the same settings, the above settings can be omitted.
Figure 29.6 Header Field Reception Flowchart Example (1)
REJ09B0441-0010 Rev.0.10 Jul 30, 2008
Page 635 of 809