R8CL35A Datasheet, PDF (622/848 Pages) Renesas Technology Corp – RENESAS MCU R8C FAMILY / R8C/Lx SERIES

Under development ^{Preliminary specification}
Specifications in this manual are tentative and subject to change.
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
27. Synchronous Serial Communication Unit (SSU)
27.5 Operation in 4-Wire Bus Communication Mode
In 4-wire bus communication mode, a 4-wire bus consisting of a clock line, a data input line, a data output line, and
a chip select line is used for communication. This mode includes bidirectional mode in which the data input line
and data output line function as a single pin.
The data input line and output line change according to the settings of the MSS bit in the SSCRH register and the
BIDE bit in the SSMR2 register. For details, refer to 27.3.2.1 Association between Data I/O Pins and SS Shift
Register. In this mode, the clock polarity, phase, and data settings are performed by using bits CPOS and CPHS in
the SSMR register. For details, refer to 27.3.1.1 Association between Transfer Clock Polarity, Phase, and Data.
When this MCU is set as the master device, the chip select line controls output. When the synchronous serial
communication unit is set as a slave device, the chip select line controls input. When it is set as the master device,
the chip select line controls output of the SCS pin or controls output of a general port according to the setting of the
CSS1 bit in the SSMR2 register. When the MCU is set as a slave device, the chip select line sets the SCS pin as
input by setting bits CSS1 and CSS0 in the SSMR2 register to 01b.
In 4-wire bus communication mode, the MLS bit in the SSMR register is set to 0 and communication is performed
MSB first.
REJ09B0441-0010 Rev.0.10 Jul 30, 2008
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