R8CL35A Datasheet, PDF (626/848 Pages) Renesas Technology Corp – RENESAS MCU R8C FAMILY / R8C/Lx SERIES

Under development ^{Preliminary specification}
Specifications in this manual are tentative and subject to change.
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
27. Synchronous Serial Communication Unit (SSU)
27.5.3 Data Reception
Figure 27.12 shows an Example of Synchronous Serial Communication Unit Operation during Data Reception
(4-Wire Bus Communication Mode). During data reception, the synchronous serial communication unit
operates as described below.
When the MCU is set as the master device, it outputs a synchronous clock and inputs data. When the MCU is
set as a slave device, it outputs data synchronized with the input clock while the SCS pin is low-input state.
When the MCU is set as the master device, it outputs a receive clock and starts receiving by performing a
dummy read from the SSRDR register.
After 8 bits of data are received, the RDRF bit in the SSSR register is set to 1 (data in the SSRDR register) and
receive data is stored in the SSRDR register. When the RIE bit in the SSER register is set to 1 (RXI and OEI
interrupt requests enabled) at this time, an RXI interrupt request is generated. When the SSRDR register is read,
the RDRF bit is automatically set to 0 (no data in the SSRDR register).
Read the receive data after setting the RSSTP bit in the SSCRH register to 1 (receive operation is completed
after receiving 1-byte data). The synchronous serial communication unit outputs a clock for receiving 8 bits of
data and stops. After that, set the RE bit in the SSER register to 0 (reception disabled) and the RSSTP bit to 0
(receive operation is continued after receiving 1-byte data) and read the receive data. When the SSRDR register
is read while the RE bit is set to 1 (reception enabled), a receive clock is output again.
When the 8th clock rises while the RDRF bit is set to 1, the ORER bit in the SSSR register is set to 1 (overrun
error: OEI) and the operation is stopped. When the ORER bit is set to 1, reception cannot be performed.
Confirm that the ORER bit is set to 0 before restarting reception.
The timing at which bits RDRF and ORER are set to 1 varies depending on the setting of the CPHS bit in the
SSMR register. Figure 27.12 shows when bits RDRF and ORER are set to 1.
When the CPHS bit is set to 1 (data download at odd edges), bits RDRF and ORER are set to 1 at some point
during the frame.
The sample flowchart is the same as that for the clock synchronous communication mode (refer to Figure 27.8
Sample Flowchart of Data Reception (MSS = 1) (Clock Synchronous Communication Mode)).
The data transfer length can be set from 8 to 16 bits using the SSBR register.
REJ09B0441-0010 Rev.0.10 Jul 30, 2008
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