R8CL35A Datasheet, PDF (465/848 Pages) Renesas Technology Corp – RENESAS MCU R8C FAMILY / R8C/Lx SERIES

Under development ^{Preliminary specification}
Specifications in this manual are tentative and subject to change.
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
21. Timer RD
21.8.12 Timer RD Interrupt Enable Register i (TRDIERi) (i = 0 or 1) in PWM3 Mode
Address 0144h (TRDIER0), 0154h (TRDIER1)
Bit b7
b6
b5
b4
Symbol —
—
—
OVIE
After Reset 1
1
1
0
b3
IMIED
0
b2
IMIEC
0
b1
IMIEB
0
b0
IMIEA
0
Bit Symbol
Bit Name
Function
R/W
b0 IMIEA Input-capture/compare-match interrupt 0: Interrupt (IMIA) by IMFA bit disabled
R/W
enable bit A
1: Interrupt (IMIA) by IMFA bit enabled
b1 IMIEB Input-capture/compare-match interrupt 0: Interrupt (IMIB) by IMFB bit disabled
R/W
enable bit B
1: Interrupt (IMIB) by IMFB bit enabled
b2 IMIEC Input-capture/compare-match interrupt 0: Interrupt (IMIC) by IMFC bit disabled
R/W
enable bit C
1: Interrupt (IMIC) by IMFC bit enabled
b3 IMIED Input-capture/compare-match interrupt 0: Interrupt (IMID) by IMFD bit disabled
R/W
enable bit D
1: Interrupt (IMID) by the IMFD bit enabled
b4 OVIE Overflow/underflow interrupt enable bit 0: Interrupt (OVI) by OVF bit disabled
R/W
1: Interrupt (OVI) by OVF bit enabled
b5
— Nothing is assigned. If necessary, set to 0. When read, the content is 1.
—
b6
—
b7
—
21.8.13 Timer RD Counter 0 (TRD0) in PWM3 Mode
Address 0147h to 0146h
Bit b7
b6
b5
b4
b3
b2
b1
b0
Symbol —
—
—
—
—
—
—
—
After Reset 0
0
0
0
0
0
0
0
Bit b15
b14
b13
b12
b11
b10
b9
b8
Symbol —
—
—
—
—
—
—
—
After Reset 0
0
0
0
0
0
0
0
Bit
Function
b15 to b0 A count source is counted. Count operation is increment.
When an overflow occurs, the OVF bit in the TRDSR0 register is set to 1.
Setting Range R/W
0000h to FFFFh
R/W
Access the TRD0 register in 16-bit units. Do not access it in 8-bit units.
The TRD1 register is not used in PWM3 mode.
REJ09B0441-0010 Rev.0.10 Jul 30, 2008
Page 429 of 809