R8CL35A Datasheet, PDF (356/848 Pages) Renesas Technology Corp – RENESAS MCU R8C FAMILY / R8C/Lx SERIES

Under development ^{Preliminary specification}
Specifications in this manual are tentative and subject to change.
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
20.7.4 Operating Example
20. Timer RC
Count source
TRC register value
FFFFh
m
TRC register is cleared
by TRCGRA register
compare match
n
Previous value is retained
whenTSTART bit is set to
0.
Set to 0000h
by a program.
p
0000h
TSTART bit in 1
TRCMR register ₀
CSEL bit in 1
TRCCR2 register ₀
TRCIOB output
p+1
“H” output at TRCGRC
register compare match
“L” initial output
Return to initial output
when TSTART bit is set
to 0.
No change
m+1
n+1
p+1
IMFA bit in 1
TRCSR register ₀
IMFB bit in 1
TRCSR register ₀
IMFC bit in 1
TRCSR register ₀
Set to 0 by a program.
Set to 1 by
a program.
Count stops
because
CSEL bit is
set to 1.
TSTART bit
is set to 0.
“L” output at TRCGRB
register compare match
“H” output at TRCGRC register
compare match
No change
Set to 0 by a program.
Set to 0 by a program.
TRCGRB register
TRCGRD register
n
Transfer
Transfer
n
Next data
Transfer from buffer register to general register
m: Value set in TRCGRA register
n: Value set in TRCGRB register
p: Value set in TRCGRC register
The above applies under the following conditions:
• The TOB bit in the TRCCR1 register is set to 0 (initial level is low, high-level output at compare match with the TRCGRC register,
low-level output at compare match with the TRCGRB register).
• Bits TCEG1 and TCEG0 in the TRCCR2 register are set to 00b (TRCTRG trigger input disabled).
Figure 20.17 Operating Example in PWM2 Mode (TRCTRG Trigger Input Disabled)
REJ09B0441-0010 Rev.0.10 Jul 30, 2008
Page 320 of 809