R8CL35A Datasheet, PDF (630/848 Pages) Renesas Technology Corp – RENESAS MCU R8C FAMILY / R8C/Lx SERIES

Under development ^{Preliminary specification}
Specifications in this manual are tentative and subject to change.
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
28. I²C bus Interface
28. I²C bus Interface
The I²C bus interface is the circuit that performs serial communication based on the data transfer format of the Philips
I²C bus.
28.1 Introduction
Table 28.1 lists the I²C bus Interface Specifications. Figure 28.1 shows a Block Diagram of I²C bus interface, and
Figure 28.2 shows the External Circuit Connection Example of Pins SCL and SDA. Table 28.2 lists the I²C bus
Interface Pin Configuration.
* I²C bus is a trademark of Koninklijke Philips Electronics N. V.
Table 28.1 I²C bus Interface Specifications
Item
Specification
Communication formats _{• I}²_{C bus format}
- Selectable as master/slave device
- Continuous transmit/receive operation (because the shift register, transmit
data register, and receive data register are independent)
- Start/stop conditions are automatically generated in master mode.
- Automatic loading of the acknowledge bit during transmission
- Bit synchronization/wait function (In master mode, the state of the SCL
signal is monitored per bit and the timing is synchronized automatically. If
the transfer is not possible yet, the SCL signal goes low and the interface
stands by.)
- Support for direct drive of pins SCL and SDA (N-channel open-drain output)
• Clock synchronous serial format
- Continuous transmit/receive operation (because the shift register, transmit
data register, and receive data register are independent)
I/O pins
SCL (I/O): Serial clock I/O pin
SDA (I/O): Serial data I/O pin
Transfer clocks
• When the MST bit in the ICCR1 register is set to 0
External clock (input from the SCL pin)
• When the MST bit in the ICCR1 register is set to 1
Internal clock selected by bits CKS0 to CKS3 in the ICCR1 register
(output from the SCL pin)
Receive error detection • Overrun error detection (clock synchronous serial format)
Indicates an overrun error during reception. When the last bit of the next unit
of data is received while the RDRF bit in the ICSR register is set to 1 (data in
the ICDRR register), the AL bit is set to 1.
Interrupt sources
• I²C bus format .................................. 6 sources ⁽¹⁾
Transmit data empty (including when slave address matches), transmit end,
receive data full (including when slave address matches), arbitration lost,
NACK detection, and stop condition detection
• Clock synchronous serial format ...... 4 sources ⁽¹⁾
Transmit data empty, transmit end, receive data full, and overrun error
Selectable functions _{• I}²_{C bus format}
- Selectable output level for the acknowledge signal during reception
• Clock synchronous serial format
- Selectable MSB first or LSB first as the data transfer direction
Note:
1. All sources use a single interrupt vector table for the I²C bus interface.
REJ09B0441-0010 Rev.0.10 Jul 30, 2008
Page 594 of 809