R8CL35A Datasheet, PDF (559/848 Pages) Renesas Technology Corp – RENESAS MCU R8C FAMILY / R8C/Lx SERIES

Under development ^{Preliminary specification}
Specifications in this manual are tentative and subject to change.
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
25. Serial Interface (UART2)
25.2.9 UART2 Special Mode Register 4 (U2SMR4)
Address 00BCh
Bit b7
Symbol SWC9
After Reset 0
b6
SCLHI
0
b5
ACKC
0
b4
b3
b2
b1
b0
ACKD STSPSEL STPREQ RSTAREQ STAREQ
0
0
0
0
0
Bit Symbol
Bit Name
Function
R/W
b0 STAREQ _{Start condition generate bit} ⁽¹⁾
0: Clear
R/W
1: Start
b1 RSTAREQ _{Restart condition generate bit} ⁽¹⁾
0: Clear
R/W
1: Start
b2 STPREQ _{Stop condition generate bit} ⁽¹⁾
0: Clear
R/W
1: Start
b3 STSPSEL SCL, SDA output select bit
0: Start and stop conditions not output
R/W
1: Start and stop conditions output
b4
ACKD ACK data bit
0: ACK
R/W
1: NACK
b5
ACKC ACK data output enable bit
0: Serial interface data output
R/W
1: ACK data output
b6 SCLHI SCL output stop enable bit
0: Disabled
R/W
1: Enabled
b7
SWC9 SCL wait bit 3
0: SCL hold low disabled
R/W
1: SCL hold low enabled
Note:
1. This bit is set to 0 when the condition is generated.
25.2.10 UART2 Special Mode Register 3 (U2SMR3)
Address 00BDh
Bit b7
b6
b5
Symbol DL2
DL1
DL0
After Reset 0
0
0
b4
b3
b2
b1
b0
—
NODC
—
CKPH
—
X
0
X
0
X
Bit Symbol
Bit Name
Function
R/W
b0
— Nothing is assigned. If necessary, set to 0. When read, the content is undefined.
—
b1 CKPH Clock phase set bit
0: No clock delay
R/W
1: With clock delay
b2
— Nothing is assigned. If necessary, set to 0. When read, the content is undefined.
—
b3 NODC Clock output select bit
0: CLK2 set as CMOS output
R/W
1: CLK2 set as N-channel open-drain output
b4
— Nothing is assigned. If necessary, set to 0. When read, the content is undefined.
—
b5
DL0 _{SDA2 digital delay setup bit} ^{(1, 2)}
b6
DL1
b7
DL2
b7 b6 b5
0 0 0: No delay
0 0 1: 1 or 2 cycles of U2BRG count source
0 1 0: 2 or 3 cycles of U2BRG count source
R/W
R/W
R/W
0 1 1: 3 or 4 cycles of U2BRG count source
1 0 0: 4 or 5 cycles of U2BRG count source
1 0 1: 5 or6 cycles of U2BRG count source
1 1 0: 6 or 7 cycles of U2BRG count source
1 1 1: 7 or 8 cycles of U2BRG count source
Notes:
1. Bits DL2 to DL0 are used to generate a delay in SDA2 output digitally in I²C mode. In other than I²C mode, set
these bits to 000b (no delay).
2. The amount of delay varies with the load on pins SCL2 and SDA2. When an external clock is used, the amount
of delay increases by about 100 ns.
REJ09B0441-0010 Rev.0.10 Jul 30, 2008
Page 523 of 809