R8CL35A Datasheet, PDF (459/848 Pages) Renesas Technology Corp – RENESAS MCU R8C FAMILY / R8C/Lx SERIES

Under development ^{Preliminary specification}
Specifications in this manual are tentative and subject to change.
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
21. Timer RD
21.8.4 Timer RD Start Register (TRDSTR) in PWM3 Mode
Address 0137h
Bit b7
b6
b5
b4
b3
b2
b1
b0
Symbol —
—
—
—
CSEL1 CSEL0 TSTART1 TSTART0
After Reset 1
1
1
1
1
1
0
0
Bit Symbol
Bit Name
Function
R/W
b0 TSTART0 _{TRD0 count start flag} ⁽³⁾
0: Count stops ⁽¹⁾
R/W
1: Count starts
b1 TSTART1 _{TRD1 count start flag} ⁽⁴⁾
0: Count stops ⁽²⁾
R/W
1: Count starts
b2 CSEL0 TRD0 count operation select bit
0: Count stops at compare match with
R/W
the TRDGRA0 register
1: Count continues after compare match with
the TRDGRA0 register
b3 CSEL1 TRD1 count operation select bit
0: Count stops at compare match with
R/W
[not used in PWM3 mode]
the TRDGRA1 register
1: Count continues after compare match with
the TRDGRA1 register
b4
— Nothing is assigned. If necessary, set to 0. When read, the content is 1.
—
b5
—
b6
—
b7
—
Notes:
1. When the CSEL0 bit is set to 1, write 0 to the TSTART0 bit.
2. When the CSEL1 bit is set to 1, write 0 to the TSTART1 bit.
3. When the CSEL0 bit is set to 0 and the compare match signal (TRDIOA0) is generated, this bit is set to 0 (count
stops).
4. When the CSEL1 bit is set to 0 and the compare match signal (TRDIOA1) is generated, this bit is set to 0 (count
stops).
Set the TRDSTR register using the MOV instruction (do not use the bit handling instruction). Refer to 21.10.1
TRDSTR Register for Notes on Timer RD.
21.8.5 Timer RD Mode Register (TRDMR) in PWM3 Mode
Address 0138h
Bit b7
b6
b5
b4
b3
b2
b1
Symbol BFD1 BFC1 BFD0 BFC0
—
—
—
After Reset 0
0
0
0
1
1
1
b0
SYNC
0
Bit Symbol
Bit Name
Function
R/W
b0 SYNC Timer RD synchronous bit
Set to 0 (TRD0 and TRD1 operate
R/W
independently) in PWM3 mode.
b1
— Nothing is assigned. If necessary, set to 0. When read, the content is 1.
—
b2
—
b3
—
b4 BFC0 TRDGRC0 register function select bit 0: General register
R/W
1: Buffer register of TRDGRA0 register
b5 BFD0 TRDGRD0 register function select bit 0: General register
R/W
1: Buffer register of TRDGRB0 register
b6 BFC1 TRDGRC1 register function select bit 0: General register
R/W
1: Buffer register of TRDGRA1 register
b7 BFD1 TRDGRD1 register function select bit 0: General register
R/W
1: Buffer register of TRDGRB1 register
REJ09B0441-0010 Rev.0.10 Jul 30, 2008
Page 423 of 809