R8CL35A Datasheet, PDF (474/848 Pages) Renesas Technology Corp – RENESAS MCU R8C FAMILY / R8C/Lx SERIES

Under development ^{Preliminary specification}
Specifications in this manual are tentative and subject to change.
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
21. Timer RD
21.10 Notes on Timer RD
21.10.1 TRDSTR Register
• Set the TRDSTR register using the MOV instruction.
• When the CSELi (i = 0 or 1) is set to 0 (count stops at compare match between registers TRDi and
TRDGRAi), the count does not stop and the TSTARTi bit remains unchanged even if 0 (count stops) is
written to the TSTARTi bit.
When the CSELi bit is set to 0, write 0 to the TSTARTi bit to change other bits without changing the
TSTARTi bit.
To stop counting by a program, write 0 to the TSTARTi bit after setting the CSELi bit to 1. If 1 is written to
the CSELi bit and 0 is written to the TSTARTi bit is set to 0 at the same time (with one instruction), the count
cannot be stopped.
• Table 21.18 lists the TRDIOji (j = A, B, C, or D) Pin Output Level when Count Stops while the TRDIOji (j =
A, B, C, or D) pin is used for the timer RD output.
Table 21.18 TRDIOji (j = A, B, C, or D) Pin Output Level when Count Stops
Stopping Count
When the CSELi bit is set to 1, write 0 to the TSTARTi bit and the
count stops.
When the CSELi bit is set to 0, the count stops at compare match
between registers TRDi and TRDGRAi.
TRDIOji Pin Output when Count Stops
Holds the output level immediately before
the count stops.
Holds the output level after the output
changes by the compare match.
21.10.2 TRDi Register (i = 0 or 1)
• When writing the value to the TRDi register by a program while the TSTARTi bit in the TRDSTR register is
set to 1 (count starts), avoid overlapping with the timing for setting the TRDi register to 0000h, and then
write. If the timing for setting the TRDi register to 0000h overlaps with the timing for writing the value to the
TRDi register, the value is not written and the TRDi register is set to 0000h.
These notes apply when selecting the following by bits CCLR2 to CCLR0 in the TRDCRi register.
- 001b (Clear by the TRDi register at compare match with the TRDGRAi register.)
- 010b (Clear by the TRDi register at compare match with the TRDGRBi register.)
- 011b (Synchronous clear)
- 101b (Clear by the TRDi register at compare match with the TRDGRCi register.)
- 110b (Clear by the TRDi register at compare match with the TRDGRDi register.)
• When writing the value to the TRDi register and continuously reading the same register, the value before
writing may be read. In this case, execute the JMP.B instruction between the writing and reading.
Program example
MOV.W
#XXXXh, TRD0
;Write
JMP.B
L1
;JMP.B
L1:
MOV.W
TRD0,DATA
;Read
REJ09B0441-0010 Rev.0.10 Jul 30, 2008
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