R8CL35A Datasheet, PDF (426/848 Pages) Renesas Technology Corp – RENESAS MCU R8C FAMILY / R8C/Lx SERIES

Under development ^{Preliminary specification}
Specifications in this manual are tentative and subject to change.
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
21.6.2 Timer RD Control Expansion Register (TRDECR)
Address 0135h
Bit b7
b6
b5
b4
b3
b2
b1
b0
Symbol ITCLK1 —
—
— ITCLK0 —
—
—
After Reset 0
0
0
0
0
0
0
0
Bit Symbol
Bit Name
Function
b0
— Nothing is assigned. If necessary, set to 0. When read, the content is 0.
b1
—
b2
—
b3 ITCLK0 Timer RD0 fC2 select bit
0: TRDCLK input selected
1: fC2 selected
b4
— Nothing is assigned. If necessary, set to 0. When read, the content is 0.
b5
—
b6
—
b7 ITCLK1 Timer RD1 fC2 select bit
0: TRDCLK input selected
1: fC2 selected
21. Timer RD
R/W
—
R/W
—
R/W
21.6.3 Timer RD Trigger Control Register (TRDADCR)
Address 0136h
Bit
b7
b6
b5
b4
b3
b2
b1
b0
Symbol ADTRGD1E ADTRGC1E ADTRGB1E ADTRGA1E ADTRGD0E ADTRGC0E ADTRGB0E ADTRGA0E
After Reset
0
0
0
0
0
0
0
0
Bit
Symbol
Bit Name
b0 ADTRGA0E A/D trigger A0 enable bit
b1 ADTRGB0E A/D trigger B0 enable bit
b2 ADTRGC0E A/D trigger C0 enable bit
b3 ADTRGD0E A/D trigger D0 enable bit
b4 ADTRGA1E A/D trigger A1 enable bit
b5 ADTRGB1E A/D trigger B1 enable bit
b6 ADTRGC1E A/D trigger C1 enable bit
b7 ADTRGD1E A/D trigger D1 enable bit
Function
R/W
0: A/D trigger disabled
R/W
1: A/D trigger generated at compare match with
registers TRD0 and TRDGRA0
0: A/D trigger disabled
R/W
1: A/D trigger generated at compare match with
registers TRD0 and TRDGRB0
0: A/D trigger disabled
R/W
1: A/D trigger generated at compare match with
registers TRD0 and TRDGRC0
0: A/D trigger disabled
R/W
1: A/D trigger generated at compare match with
registers TRD0 and TRDGRD0
0: A/D trigger disabled
R/W
1: A/D trigger generated at compare match with
registers TRD1 and TRDGRA1
0: A/D trigger disabled
R/W
1: A/D trigger generated at compare match with
registers TRD1 and TRDGRB1
0: A/D trigger disabled
R/W
1: A/D trigger generated at compare match with
registers TRD1 and TRDGRC1
0: A/D trigger disabled
R/W
1: A/D trigger generated at compare match with
registers TRD1 and TRDGRD1
REJ09B0441-0010 Rev.0.10 Jul 30, 2008
Page 390 of 809