PD70F3826_15 Datasheet, PDF (65/75 Pages) Renesas Technology Corp – RENESAS MCU

μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
26. CLOCK MONITOR, LOW-VOLTAGE DETECTOR
26. CLM, LVI
(1) Clock monitor
The clock monitor samples the main clock by using the internal oscillation clock (fR) and generates a reset
request signal when oscillation of the main clock is stopped.
(2) Low-voltage detector
The low-voltage detector (LVI) has the following functions.
• Compares the supply voltage (VDD) and detection voltage (VLVI) and generates an interrupt request signal or
internal reset signal when VDD < VLVI.
• An interrupt request signal or internal reset signal can be selected.
• Can operate in STOP mode.
• Operation can be stopped by software.
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
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