PD70F3826_15 Datasheet, PDF (52/75 Pages) Renesas Technology Corp – RENESAS MCU

μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
The following figure shows the configuration of I²C.
17. I²C BUS
Internal bus
IIC status register n (IICSn)
IIC control register n
(IICCn)
MSTSn ALDn EXCn COIn TRCn ACKDn STDn SPDn
IICEn LRELn WRELn SPIEn WTIMn ACKEn STTn SPTn
SDA0n
Noise
eliminator
DFCn
Slave address
register n (SVAn)
Match
signal
Clear
Set
IIC shift
register n (IICn)
SO latch
D Q _CLn1,
CLn0
Start
condition
generator
Stop
condition
generator
N-ch open-drain
output
TRCn
Output control
Data
retention time
correction
circuit
ACK detector
Start condition
detector
ACK
generator
Wakeup controller
SCL0n
Noise
eliminator
Stop condition
detector
Serial clock counter
DFCn
N-ch open-drain
output
Prescaler
Serial clock
controller
fxx
fxx to fxx/5
Interrupt request
signal generator
Serial clock
wait controller
IICSn.MSTSn,
EXCn, COIn
IIC shift
register n (IICn)
IICCn.STTn, SPTn
IICSn.MSTSn, EXCn, COIn
Prescaler
INTIICn
Bus status
detector
OCKSENn OCKSTHn OCKSn1 OCKSn0 CLDn DADn SMCn DFCn CLn1 CLn0 CLXn
STCFn IICBSYn STCENn IICRSVn
IIC division clock select
register n (OCKSn)
IIC clock select
register n (IICCLn)
IIC function expansion
register n (IICXn)
Internal bus
IIC flag register n
(IICFn)
Remark fXX: Main clock frequency
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 52 of 75