PD70F3826_15 Datasheet, PDF (26/75 Pages) Renesas Technology Corp – RENESAS MCU

μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
2. CPU FUNCTIONS
2. CPU FUNCTIONS
The CPU of the V850ES/JE3-E, V850ES/JF3-E and V850ES/JG3-E is based on RISC architecture and executes
most instructions in a 1-clock cycle by using a 5-stage pipeline.
The features of the CPU are as follows.
{ Minimum instruction execution time: 20 ns (@ 50 MHz operation with main clock (fXX))
30.5 μs (@ 32.768 kHz operation with sub-clock (fXT))
{ Memory space Program space: 64 MB linear
Data space:
4 GB linear
{ General-purpose registers: 32 bits × 32 registers
{ Internal 32-bit architecture
{ 5-stage pipeline control
{ Multiplication/division instructions
{ Saturation operation instructions
{ 1-clock 32-bit shift instruction
{ Load/store instructions with long/short format
{ Internal memory
Generic Name
V850ES/JE3-E
V850ES/JF3-E
V850ES/JG3-E
Table 2-1. ROM/RAM
Products
Flash Memory Size
μPD70F3826
μPD70F3827
μPD70F3828
μPD70F3829
μPD70F3830
μPD70F3831
μPD70F3832
μPD70F3833
μPD70F3834
μPD70F3835
μPD70F3836
μPD70F3837
64 KB
128 KB
256 KB
256 KB
64 KB
128 KB
256 KB
256 KB
64 KB
128 KB
256 KB
256 KB
RAM Size
Internal RAM Data RAM
16 KB
16 KB
32 KB
16 KB
48 KB
16 KB
48 KB
16 KB
16 KB
16 KB
32 KB
16 KB
48 KB
16 KB
48 KB
16 KB
16 KB
16 KB
32 KB
16 KB
48 KB
16 KB
48 KB
16 KB
{ Four types of bit manipulation instructions
• SET1
• CLR1
• NOT1
• TST1
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
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