PD70F3826_15 Datasheet, PDF (3/75 Pages) Renesas Technology Corp – RENESAS MCU

μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
Function list (V850ES/JF3-E)
Generic Name
V850ES/JF3-E
Product Name
μPD70F3830
μPD70F3831
μPD70F3832
μPD70F3833
Internal Flash memory
64 KB
128 KB
256 KB
256 KB
memory Internal RAM
16 KB
32 KB
48 KB
48 KB
Data RAM
16 KB
16 KB
16 KB
16 KB
Memory space
64 MB
General-purpose register
32 bits × 32 registers
Clocks Main clock oscillation PLL mode : fX = 3 to 6.25 MHz, fXX = 24 to 50 MHz (multiplication by 8)
Clock through mode : fX = 3 to 6.25 MHz ( internal : fXX = 3 to 6.25 MHz)
Subclock oscillation fXT = 32.768 kHz
Internal oscillation
fR = 220 kHz (TYP.)
Minimum instruction 20 ns (@ 50 MHz operation with main system clock (fXX))
execution time
I/O ports
I/O: 42 (5 V tolerant : 28)
Timer
16-bit TAA
5 channels
16-bit TAB
1 channel
16-bit TMM
4 channels
16-bit TMT
1 channel
Motor control
1 channel
Watch timer
1 channel (RTC)
WDT
1 channel
Real-time output function
6 bits × 1 channel
10-bit A/D converter
10 channels
Serial
CSIF/UARTC
1 channel
interface CSIF/UARTC/I²C 2 channels
CSIF
UARTC/I²C
UARTC/I²C/CAN
1 channel
−
−
−
1 channel
USB function
1 channel
Ethernet controller
1 channel
DMA controller
4 channels (transfer target: on-chip peripheral I/O, internal RAM)
Interrupt
External ^{Note 1, 2}
19(19)
19(19)
19(19)
19(19)
source
Internal
57
57
57
61
Power-save function
HALT/IDLE1/IDLE2/STOP/subclock/sub-IDLE modes
Reset factor
RESET pin input, watchdog timer 2 (WDT2), clock monitor (CLM), low-voltage detector (LVI)
On-chip debugging
MINICUBE, MINICUBE2 supported
Operating supply voltage
2.85 to 3.6 V
Operating ambient temperature −40 to +85°C
Package
80-pin plastic LQFP (fine pitch) (12 × 12 mm)
Notes 1. The figure in parentheses indicates the number of external interrupts that can release the STOP mode.
Notes 2. Include NMI.
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
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